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PCM9211: DIR Behavior During Occuring Preamble Error

Sadanori Kato
Guru 36540 points
Part Number: PCM9211

Hi,

The frequency of the clocks(SCKO, BCK and LRCK) which are generated by DIR changes if a error is included in the preamble data.
So, could you please tell me if there is a way to reduce the frequency variation of the extracted clock ?
(e.g.: changing the constant of the loop filter, changing the register settings and so on)

Best regards,
Kato

  • 0
    TI__Expert 5645 points

    Hi Kato-san,

    As you know, PCM9211 has on-chip PLL (including a voltage-controlled oscillator, or VCO) for recovering the clock from the S/PDIF input signal & In PLL mode, the output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock. The variation of the output freq is a function of PLL jitter. In general, the DIR module has excellent jitter reduction and meets/exceeds the jitter tolerance spec defined by IEC60958-3.

    What kind of variation are you observing? Thanks.


    Best regards,
    Ravi 

  • 0 in reply to Ravi Patil
    Guru 36540 points

    Hi Ravi-san,

    Thank you for your reply.

    The frequency for the SCKO clock changes by a few percent if insert one bit error data to the preamble data, so please tell me how to reduce the frequency variation.

    Best regards,
    Kato

  • 0 in reply to Sadanori Kato
    Guru 36540 points

    Hi Ravi-san,

    Should we consider that your team cannot support PCM9211 ?

    Best regards,
    Kato