TLV320AIC3256: What's the realtionship among the asmple rates, interpolation and decimation?

user5330283

Part Number: TLV320AIC3256

There are so many sample rates. I’m puzzled about the relationship among the sample rates, interpolation and decimation.

I configurate the NADC, MADC, AOSR to get the first sample rate, ADC_Fs.

And configurating the NDAC, MDAC, DOSR, I get the second sample rate, DAC_Fs.

In the PPS, there is the third sample rate, CurrentRate.

On WCLK pin, there is the forth sample rate, WCLK, which is I2S sample rate.

I guess that:

ADC_Fs / decimation = DAC_Fs / interpolation = CurrentRate = WCLK.

Is that right?

I want the ADC_Fs = 192kHz, WCLK = 44.1kHz.

As for DAC_Fs, 192kHz or 44.1kHz is OK.

How can I set those sample rate, interpolation and decimation?

In fact, I got some noise from my device with the process flow which was work well on the EVM.

These are 3 differences between the EVB and my device.

On the EVM, the input channels are IN1L/R. On my device, they are IN3L/R. I’ve changed the routing register in my code.
The XTAL oscillator on EVB is 12.288MHz, which on my device is 24MHz. I’ve changed the J=8, D=1920, P=2, R=1 to make the PLL_CLOCK = 98.304MHz, which was same as PLL_CLOCK on EVM.
The BCLK on EVM is 2.822 4MHz, and the BCLK on my device is 1.411 2MHz. I read the register 27 on page 0, and the value is 0x00, which means I2S 16bit, no matter on EVM or on my device. On EVM, although the BCLK=2*32*WCLK, the least 16bit on DIO is always 0x00.

Which can cause the noise? Or something else I missed?

over 7 years ago

0 Diego Melendez over 7 years ago

TI__Guru 57800 points

Hi,

The sampling rates from the ADC, DAC and word clock should be the same, so it is possible that the configuration of the device to operate in a higher sampling rater while receiving a lower WCLK is causing some noise.

Can you make sure the WCLK on your system has the same sampling rate determined by PPS?. The exported file should have the rate on the name: base_main_RateXX.

In general, the changes between the EVM and your system should not affect with noise, however, I'd like to make sure the clocks are correctly configured. Can you please read the clock registers after the device in your board is configured so I can check if the clock settings are fine?.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 user5330283 over 7 years ago in reply to Diego Melendez

Prodigy 100 points

Diego,

Thank you for your patient answering! But I still don't understand the relationship among them.

First, answer your suggestion.

I'm sure the WCLK on my system has the same sampling rate determined by PPS. I use the file named base_main_Rate44, and detect the WCLK pin to make sure the singal on WCLK is 44.1KHz.

I read registers configured, and only the register 124 on page 1 is not equal to what I write. The write is 0x16, and the read is 0x06. (In face, there are other unequal, such as register 8 on page 80. They are all miniDSP registers, and it's normal in these registers that write and read is not equal.)I also attend to make the MFP4 pin to ouput the PLL_CLOCK, and the signal is equal to what I set.

Then, say about my puzzle.

For example, the ADC_Fs is 192KHz, and the decimation factor is 4x. So the sampling data after ADC is 192KHz, but after the sampling data has passed the decimation filter, the data will be change to 192/4 = 48KHz. If the WCLK is 192KHz which means I2S data is 192KHz ，the data after decimation filter and I2S data will not match.

And the DAC has the similar issue.

What's the mistake in my statement? Maybe I misunderstood how the decimation filter and interpolation filter work？

Thanks again!

0 Diego Melendez over 7 years ago in reply to user5330283

TI__Guru 57800 points

Hi,

The decimation and interpolation filters are internal to the ADC and DAC structure respectively; there is no interpolation filter on the ADC as there is no decimation filter in the DAC

Even if the data is passed between them in PPS with an interprocessor block, there is no change in the signal sampling as it will follow WCLK frequency.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

Audio

Audio forum

TLV320AIC3256: What's the realtionship among the asmple rates, interpolation and decimation?