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TPA2008D2: TPA2008 PWM Stability Issue with DGND and AGND Ground Loop

Wayne Chen (ex FAE)
Guru 15950 points
Part Number: TPA2008D2

Hi Sirs,

According to the TPA2008 datasheet, the TPA2008's COSC and ROSC are refer to AGND. With separated AGND and DGND designs, customer found that the junction location of AGND and GND' impact PWM output's stability in high temperature.

Location A and C -> High jitter with Class-D PWM output, high noise when TPA2008's temperature goes up
Location B (blue wired a AGND trace to location B) -> Stable Class-D PWM output in entire temperature range.

There is no COSC derating problem in high temperature. Would you pls advise the relationship between AGND/GND loops and PWM stability? Can we avoid jitter problem in high temperature with a big, single GND plan for TPA2008?   



Thank you and Best regards,

Wayne Chen
05/17/2018

  • 0
    Guru 140200 points
    Hi Wayne,

    follow exactly the recommendations given in the EVM appnote. Take the layout of EVM as reference for your one layout. Think about where the noisy currents are flowing. The loudpseaker outputs are very noisy and will produce large ground return currents in the ground plane at the bottom side of PCB. These currents will flow back to the decoupling caps of PVDD and to PGND. This ground current path should not be shared with circuitry being connected to AGND like the volume pot, C6 and R2. Look how this AGND ground is connected to the GND terminal of PCB forming a ground star point there. No Loudspeaker ground return current should run along this ground connection.

    Kai
  • 0
    TI__Mastermind 20085 points
    Hi Wayne,

    The Analog ground (AGND) and Digital ground (DGND) must be connected at one point of the circuit, but they should have different layer or plane.
    It is always recommended to have one plane on the ground as big as possible to the power dissipation.
    This seems to be a decoupling problem. The TPA2008D2 requires adequate power supply decoupling to ensure a high-efficiency operation with low total harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 μF, within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency transients, spikes, or digital hash on the line. In addition to the 0.1 μF ceramic capacitor, it is recommended to place a 2.2 μF to 10 μF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy faster than the board supply, thus helping to prevent any drop in the supply voltage.
    You should also follow given guidelines on the Special Layout Considerations section of the amplifier's datasheet.

    Best Regards
    José Luis Figueroa
    Audio Applications Engineer
  • 0 in reply to José Luis
    Guru 15950 points
    Thank you for your elaboration, Luis...Wayne Chen