Programming AIC3254 in a real system

Micky52259

Hi,

I've made up an application with PPS with the EVM-U kit. This is running and working fine (at least, if I add one own I2C Setup file). I choose the 24 kHz sampling rate, as my out shall work at this frequency.

Now I want to download this app into my more real world: I have a DSP (c5515) in chain after the aic3254. In a "aic3204" mode this chip is running at 24kHz sample rate as shown in the code shown below: This runs and works, too. The Clk Signal is comming derived from the I2S bus and it means, that the samples are arriving with resulting 24 kHz in my DSP memory. I observed, that the aic32x4 is sending data rates different from sample rates. Eg. when just changing MDAC/NDAC and MADC/NADC the sample rate is changed (hearing the audio quality at e.g. 24 kHz ) but the data is still sent with 48 kHz, if the I2S Bus is not changing.

Now I want to download the PPS Applikation. I've used the miniDSP Registersets of the PPS-headerfile, miniDSP_D_reg_values and miniDSP_A_reg_values after this setip

(my function vfnSet_AIC() works with the I2C Interface), after the the AIC setup, but then noting is at the output.

I've also tested the programming of the register-set given by PPS: First the reg_value REG_Section_program[], then the miniDSP registers, afterwards the I2C Registers of my own Commandfile for the EVM-U. I adapted the registers for the clock, as this is of course different in the EVM-U. I also wonder, if the I2S clock is somehow important for th operation of the minidsp.

Here my registers of the "AIC3204-mode".

// ------------------ Configuring the AIC3254 as if an AIC3204 Device => this works -------//

//* Configure AIC3204 */
    vfnSet_AIC( 0, 0x00 );      // Select page 0
    vfnSet_AIC( 1, 0x01 );      // Reset codec
    vfnSet_AIC( 0, 0x01 );      // Point to page 1
    vfnSet_AIC( 1, 0x08 );      // Disable crude AVDD generation from DVDD
    vfnSet_AIC( 2, 0x00 );      // Enable Analog Blocks
    // PLL and Clocks config and Power Up
    vfnSet_AIC( 0, 0x00 );      // Select page 0
    vfnSet_AIC( 27, 0x00 );      // BCLK and WCLK is set as i/p to AIC3204(Slave)
    vfnSet_AIC( 4, 0x07 );      // PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK
    vfnSet_AIC( 6, 0x20 );      // PLL setting: J=32
    vfnSet_AIC( 7, 0 );         // PLL setting: HI_BYTE(D = 0)
    vfnSet_AIC( 8, 0 );         // PLL setting: LO_BYTE(D) = 0
    // For 24 KHz sampling
    vfnSet_AIC( 5, 0x92 );      // PLL setting: Power up PLL, P=1 and R=2
    vfnSet_AIC( 13, 0x00 );      // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
    vfnSet_AIC( 14, 0x80 );      // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
    vfnSet_AIC( 20, 0x80 );      // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6 (War 0x88)
    //
    //
    vfnSet_AIC( 11, 0x88 );      // Power up NDAC and set NDAC value to 8
    vfnSet_AIC( 12, 0x82 );      // Power up MDAC and set MDAC value to 2
    vfnSet_AIC( 18, 0x88) ;      // Power up NADC and set NADC value to 8
    vfnSet_AIC( 19, 0x82 );      // Power up MADC and set MADC value to 2
    vfnSet_AIC( 61, 0x03 );      // Filtertyp 3 des ADC
    // DAC ROUTING and Power Up
    vfnSet_AIC( 0, 0x01 );      // Select page 1
    vfnSet_AIC( 12, 0x08 );      // LDAC AFIR routed to HPL
    vfnSet_AIC( 13, 0x08 );      // RDAC AFIR routed to HPR
    vfnSet_AIC( 0, 0x00 );      // Select page 0
    vfnSet_AIC( 64, 0x02 );      // Left vol=right vol
    vfnSet_AIC( 65, 0x00 );      // Left DAC gain to 0dB VOL; Right tracks Left
    vfnSet_AIC( 63, 0xd4 );      // Power up left,right data paths and set channel
    vfnSet_AIC( 0, 0x01 );      // Select page 1
    vfnSet_AIC( 16, 0x06 );      // Unmute HPL , 6dB gain
    vfnSet_AIC( 17, 0x06 );      // Unmute HPR , 6dB gain
    vfnSet_AIC( 9, 0x30 );      // Power up HPL,HPR
    vfnSet_AIC( 0, 0x00 );      // Select page 0
    vfnPause(8000);
    vfnSet_AIC( 0, 0x01 );      // Select page 1
    vfnSet_AIC( 51, 0x40 );      // SetMICBIAS
    vfnSet_AIC( 52, 0xc0 );      // STEREO 1 Jack-> IN2_L to LADC_P through 40 kohm
    vfnSet_AIC( 55, 0xc0 );      // IN2_R to RADC_P through 40 kohmm
    vfnSet_AIC( 54, 0x03 );      // CM_1 (common mode) to LADC_M through 40 kohm
    vfnSet_AIC( 57, 0xc0 );      // CM_1 (common mode) to RADC_M through 40 kohm
    vfnSet_AIC( 59, 0x1f );      // Gain L/R 95*0,5 dB= 47,5 dB (Maximumwert
    vfnSet_AIC( 60, 0x1f );      //
    vfnSet_AIC( 0, 0x00 );      // Select page 0
    vfnSet_AIC( 81, 0xc0 );      // Powerup Left and Right ADC
    vfnSet_AIC( 82, 0x00 );      // Unmute Left and Right ADC
    vfnSet_AIC( 0, 0x00 );

over 14 years ago

0 Hui.Li over 14 years ago

TI__Expert 4645 points

Hi Micky,

Let me rephrase your question just to make sure I understand it correctly.

Your real world system is --- you have an AIC3254 followed by DSP (c5515). You are using AIC3254 to convert analog input (IN2L/R) into I2S and sending this I2S Data into DSP(c5155). Your DSP is I2S Master because it sends MCLK, BCLK and WCLK into AIC3254. Because this WCLK is 24 KHz, you need to sample the data at Fs = 24 KHz inside AIC3254. Is this correct? If so, what is the rate of your MCLK and BCLK that are coming from DSP?? Also, is it 16 bits or 24 bits?

when you say you use the script to program AIC3254 as if it is AIC3204, do you mean that you're using processing block instead of miniDSP?

But when you combine the script with miniDSP code generated by PPS, you don't see any DOUT, is it corret?

If you can, please help me clarify my questions above and send me two files -- 1) the script that you use to program AIC3254 as if it is AIC3204, that is, without miniDSP code 2) And the process flow you use to program the miniDSP.

Once I have these two files, I will combine them and test it out on my side. Thanks!

Regards,

Hui

0 Micky52259 over 14 years ago in reply to Hui.Li

Intellectual 765 points

Hi Hui,

>Your real world system is --- you have an AIC3254 followed by DSP (c5515). You are using AIC3254 to convert analog input (IN2L/R) into I2S and sending this I2S Data into DSP(c5155).

Yes that's right. In fact, the system c5515 and aic3254 is exactly as the c5515 EVM (see http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=239), except, that I have an aic3254 instead of the aic3504. Here the connection of the EVM, just exchange the aic3204 with the aic3254.

I measured the BCLK with an osci with 770 kHz and the WCLK with 24.1 kHz.

EDIT: I don't have an MCLK, it's connected, but there is no clock on this pin. Is this ok?

>Your DSP is I2S Master because it sends MCLK, BCLK and WCLK into AIC3254. Because this WCLK is 24 KHz, you need to sample the data at Fs = 24 KHz inside AIC3254. Is this correct? If so, what is the rate of your MCLK and BCLK that are coming from DSP?? Also, is it 16 bits or 24 bits?

Yes, your right. My DSP is running at 100 MHz, Master and 16 Bit, stereo. The DSP I2S is configured as:

   sAICConfig.dataType         = I2S_STEREO_ENABLE;
    sAICConfig.loopBackMode     = I2S_LOOPBACK_DISABLE;
    sAICConfig.fsPol             = I2S_FSPOL_LOW;
    sAICConfig.clkPol            = I2S_RISING_EDGE;
    sAICConfig.datadelay        = I2S_DATADELAY_ONEBIT;
    sAICConfig.datapack            = I2S_DATAPACK_ENABLE;
    sAICConfig.signext            = I2S_SIGNEXT_DISABLE;
    sAICConfig.wordLen            = I2S_WORDLEN_16;
    sAICConfig.i2sMode            = I2S_MASTER;
    sAICConfig.clkDiv            = I2S_CLKDIV128;
    sAICConfig.fsDiv            = I2S_FSDIV32;
    sAICConfig.FError            = I2S_FSERROR_DISABLE;
    sAICConfig.OuError            = I2S_OUERROR_DISABLE;

1) the script that you use to program AIC3254 as if it is AIC3204, that is, without miniDSP code

You can find the settings of the registers above in my first mail - with this progamming I can read data at my DSP and write them back to the DSP.

Here a very simple thing to start with: I tried to download this, but this doesnot work. I used the purepath driver, frist programming the setup and then the miniDSP A and D. Is this the right way?

I changed the registers as follows for CLK:
    { 0,0x00},
//            # reg[ 0][ 5] = 0x91    => changed/differs from orginal
    { 5,0x92},
//            # reg[ 0][ 6] = 0x08    => changed/differs from orginal
    { 6,0x20},
//            # reg[ 0][ 7] = 0x00    ; D=0000 (MSB)
    { 7,0x00},
//            # reg[ 0][ 8] = 0x00    ; D=0000 (LSB)
    { 8,0x00},
//            # reg[ 0][ 4] = 0x03    => changed/differs from orginal
    { 4,0x07},
//            # reg[ 0][254] = 0x0a    ; Delay 10ms for PLL to lock
    {254,0x0A},
//            # reg[ 0][ 12] = 0x88    => changed/differs from orginal
    { 12,0x82},
//            # reg[ 0][ 13] = 0x01    => changed/differs from orginal
    { 13,0x00},
//            # reg[ 0][ 14] = 0x00   => changed/differs from orginal
    { 14,0x80},
//            # reg[ 0][ 18] = 0x02   => changed/differs from orginal
    { 18,0x88},
//            # reg[ 0][ 19] = 0x90   => changed/differs from orginal
    { 19,0x82},
//            # reg[ 0][ 20] = 0x80    ; AOSR = 128
    { 20,0x80},
//            # reg[ 0][ 11] = 0x82    ; NDAC = 2, divider powered on
    { 11,0x88},

The first thing is, if you just can provide a small File, which works for this PPS Element.

0 Micky52259 over 14 years ago in reply to Micky52259

Intellectual 765 points

Hi Hui,

In the meantime I think I've found a first problem:The PLL must be set so, that the internal CLK is 98 MHz and the OSR has to be identical.

I will now try to download my real pps Application and tell if succeeding.

regards.

Micky

0 Hui.Li over 14 years ago in reply to Micky52259

TI__Expert 4645 points

Hi Micky,

Please see the attached process flow. In the PPS interface, if you click the framework, you will see "SystemSettingsCode" under the properties window on the right.

Inside this "systemSettingsCode", I have made changes so that it configure the codec in the following way:

It takes Analog input at IN2L and IN2R, convert it into I2S data at Fs = 24 KHz and send it to DSP through I2SOUT.

In the meantime, it takes I2S data from DSP through I2SIN and convert it back to Analog output.

Since you don't have any clock on the MCLK pin, I take the 770 KHz BCLK as the system clock for AIC3254. That is, the PLL inside AIC3254 is taking in this 770 KHz clock and derive other clocks from there.

All the details are included in the "SystemSettingCode". Please let me know if this applies to your application.

Regards,

Hui

ProcessFlow2.pfw

0 Hui.Li over 14 years ago in reply to Hui.Li

TI__Expert 4645 points

HI Micky,

please ignore the previous process flow and use this C5155.pfw

/Hui

C5155.pfw

0 Micky52259 over 14 years ago in reply to Hui.Li

Intellectual 765 points

Hi Hui,

indeed this piece of code was the solution:

; Take 770 KHz BCLK as PLL input clock
; R=4, P=1, J=32, power up PLL
    reg[ 0][ 6] = 0x20;
    reg[ 0][ 4] = 0x07;
    reg[ 0][ 5] = 0x94;

Perhaps it would be worth to document somewhere, that the resulting PLL output Clock should be 98 MHz for the miniDSP operation.

Thanks for your help!

Micky

0 Hui.Li over 14 years ago in reply to Micky52259

TI__Expert 4645 points

I am glad it works!

thanks for the suggestions. As a matter of fact, the PLL clock configuration varies a lot application by application.

In your specific application, since you don't have MCLK, we take the BCLK as the PLL input clock. The codec_CLKIN doesn't need to be 98 MHz, however it cannot go over 110 MHz.

I think what we really need to document is a few case studies that demonstrate how to configure the clocks. Attached is an app note wrriten by my colleague, which covers part of this discussion.

/Hui

AIC3254_Design_configuration.pdf

0 Hui.Li over 14 years ago in reply to Hui.Li

TI__Expert 4645 points

Hi Micky,

Please also see the attached for PLL clock rate constraints. It's taken from AIC3254 datasheet.

/Hui

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Programming AIC3254 in a real system