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TLV320ADC3101: Question of TLV320ADC3101 Settings for DMIC Input to TDM Output

Wayne Chen (Audio AE)
Genius 15950 points
Part Number: TLV320ADC3101

Hi Sirs,

We are supporting customer to program the TLV320ADC3101 to convert DMIC input (pin 19, pin20) to TDM output. We saw DMIC configuration tabs in the GUI however, there is no TDM option in the ASI page. Would you pls advise the process to configure the TLV320ADC3101's ASI to TDM? 






Thank you and Best regards,

Wayne Chen
06/07/2018

  • 0
    TI__Guru 57800 points

    Hi, Wayne,

    In order to configure the device in TDM mode, it is only required to set the audio interface to DSP mode, assuming the bit clock provided to the device has a frequency larger than N×Data_size×Fs, where FN is th enumber of channels in the TDM bus.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    TI__Genius 15950 points
    Hello Diego,

    Thanks a lot. May we have tips of PLL configuration for the following configuration?

    BCK = 32 * 2 *8K
    MCK = 256 * 8K;

    Thank you and Best regards,

    Wayne Chen
    06/12/2018
  • 0 in reply to Wayne Chen (Audio AE)
    TI__Guru 57800 points

    Hi, Wayne,

    Based on the information provided, I assume the ADC3101 is configured as the I²S master and the sampling rate is 8KHz, correct?. If so, the following clock configurations would be required.

    MCLK input = 2.048MHz

    CODEC_CLKIN = MCLK
    NADC = 1
    MADC = 2
    AOSR = 128
    BDIV_CLKIN = ADC_CLK
    BCLK N divider = 4

    Please note that PLL is not used with this application as only the NADC and MADC dividers can be used to generate the 8KHz sampling rate. With this configuration, a  1.024MHz clock will be provided as the DMIC clock, which should be fine for a typical digital microphone.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    TI__Genius 15950 points
    Hello Diego,

    Customer wrote CFG follow up ADC3101 application note at www.ti.com/.../slaa508.pdf, still got flat DMCLK and DOUT output. Would you pls assist us to check if there is missing or mistake?

    ------------------------------------------------------------------------------------------------------------
    w 30 01 01 # Software Reset
    w 30 00 00 # Select Page 0
    w 30 04 0F # Clock-Gen Multiplexing - logic level 0 & PLL_CLK (generated on-chip)
    w 30 26 03 # early_3-state enabled & time_slot_mode enabled
    w 30 35 12 # Enable DOUT Pins

    #Digital Microphone Setting
    w 30 33 28 #Select DMCLK pin as Digital Microphone clock
    w 30 34 04 #Select DMDIN pin as digital mic data in
    w 30 50 02 #Left channel on falling edge, Right channel on rising edge.
    w 30 51 CC #Turn ADCs on and Enable Digital Microphone
    w 30 52 00 #Unmute both ADCs
    ------------------------------------------------------------------------------------------------------------

    Thank you and Best regards,

    Wayne Chen
    06/21/2018
  • 0 in reply to Wayne Chen (Audio AE)
    TI__Guru 57800 points

    Hi, Wayne,

    I revised the code and it seems the issue iw related to the clock configuration, specifically register 4. It is being configured to use a logic '0' as PLL input and use the PLL as the source of the internal clock tree, which will result in no clock running internally. Based on the previous responses, the correct setting for register 4 would be 0x00 (or 0x0C if they want to connect the PLL input to logic 0).

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer