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PCM1795: Multiple PCM1795 I2S Clock/Data Distribution

Part Number: PCM1795
Other Parts Discussed in Thread: PCM1690, , TIDA-01414

Hello,

Currently I'm designing an USB DAC with 10 analogue Outputs, 2 analogue Inputs and 6 digital Inputs.

To archieve this I want to run a XMOS chip (XUF 216). The XMOS has a maximum of 32ch I/O via I2S; in the case of the full 32ch it works via TDM. Around the XMOS Chip I want to use TI hardware to get the analogue outputs and inputs. Because the XMOS is the Master, for the 6 digital Inputs there is the need of asynchronous sample rate converters, in this case SRC4192s. So for 6 channels I need 3 SRC4192s. To get the 2 analogue Inputs I want to use a 2 channel ADC. The main goal of the board is to get the maximum sound quality out of the DACs. At first I just wanted to use two PCM1690, so I can easyly get my 10 channels  with two chips only. But I have read, that the PCM1795 is much better at performing and has 32bit, what is very helpful for DSP Processing (Active Crossover, Room Correction and Digital Volume Control). If I go for the PCM1795s I would need at least 5 of them. So there are 5 DACs + 1 ADCs + 3 ASRCs + 1 XMOS Chip. That means I need to distribute the MCLK to 10 chips and the LRCK,BCLK to 9 chips. But how to archieve this? With clock drivers and clock buffers? Would there be a degradation of sound quality when using them and/or additive jitter? And how to route the clocks? Daisy chain? with a bus? or star chained with the buffers like in the dolby atmos soundbar reference design? How to deal with reflections etc?

Thank You very much!

Jens

  • Hi Jens,

    In general, I would recommend a clock buffer with a star topology.  The TIDA-01414 Dolby Atmos Soundbar TI Design is a really good example of this.

    The small series resistor for each branch will help reduce reflections as well.

    Let me know if you have more questions,

    Thanks!

    Paul

  • Thank You very much Paul!

    I see in the Design, that for example the SCK is split 6 times. At first it is split 2 times and then goes through the clock driver and is then split 3 times. This equals 6. How do I now archieve a 10 split. Do I first split 3 times and then again every lane 3 times (one of them 4 times) through a clock driver? Or do I just increase the number after the driver (2 split then lanes through driver and then split 5 times?

    Thank you and kind regards
    Jens
  • I don't know if there is a hard-and-fast rule for this. I think PCB layout would have more of an impact. I would recommend you buffer the clock signal before it has to go a long distance geographically. Maybe have a few buffers at the clock origin, one going to the ADCs and one to the DACs, then have another buffer locally to each, with splits there.

    Thanks!
    Paul