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Linux/TLV320AIC3262: DAC/ADC Sample rate

Bruce Lip
Prodigy 40 points

Part Number: TLV320AIC3262

Tool/software: Linux

Hello,

     I have a device that inputs 32bit - I2S in with the following sample rates: 384kHz. 

     But the TLV320AIC3262's datasheet write that : "The TLV320AIC3262 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. "

     We need a sample rates over 384kHz for ADC/DAC.  So I want to ask if TLV320AIC3262 can meets our needs?  If it is, and How to set regiseter to meets our needs ?

thanks.

  • 0
    TI__Guru 57800 points

    Hi, Bruce,

    Welcome to E2E, Thanks for your interest in our products!.

    As the datasheet says, the TLV320AIC3262 supports a maximum sampling rate of 192KHz, so operation with 384KHz is not supported by this device.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 40 points
    hello sir,
    the sampling rate of DAC is limited in its range by the following condition
    1. 2.8MHz < DOSR * DAC_FS < 6.2MHz
    2. DAC_CLKIN = NDAC*MDAC*DOSR*DAC_FS
    3. MDAC*DOSR/32 ≥ RC
    if we set MDAC=2, DSOR=16, NDAC=1, and choose PRB_P26 for DAC processing blocks , then we can get DAC_FS =384kHz. is that can works ?
    please help check it for us.
    thanks very much.
  • 0 in reply to Diego Melendez
    Prodigy 40 points
    hello sir,
    the sampling rate of DAC is limited in its range by the following condition
    1. 2.8MHz < DOSR * DAC_FS < 6.2MHz
    2. DAC_CLKIN = NDAC*MDAC*DOSR*DAC_FS
    3. MDAC*DOSR/32 ≥ RC
    if we set MDAC=2, DSOR=16, NDAC=1, and choose PRB_P26 for DAC processing blocks , then we can get DAC_FS =384kHz. is that can works ?
    please help check it for us.

    thanks very much.
  • 0 in reply to Bruce Lip
    TI__Guru 57800 points

    Hi, Bruce,

    The conditions you mention should be met in general terms, but the sampling rate limit is not determined by these parameters. The sampling rate of the codec in general is determined by the internal clocking and filter architecture. For this articular family of codecs, the filters and internal clocking structure supports a maximum sampling rate of 192KHz.

    DAC_Fs should be adjusted to match the sampling rate of the I²S bus (which comes from the WCLK);  even if you set the clock parameters as 384KHz, the device might not operate as expected as this is not a supported sampling rate. We cannot guarantee the correct performance of the codec under these conditions.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 40 points
    OK, got it and thank you very much for your reply, ^_^.