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PCM1864: BCLK/FCLK question for audio TDM function

Sam Ting
Expert 3670 points
Part Number: PCM1864


Dear sirs,

We are implementing audio TDM functions on nVidia Jetson TX2 platform, and till now we still have the troubles about BCLK/FCLK. According to nVidia, the clock should be 44100 * 2 * 16 = 1.4112 Mhz. According to TI’s spec, 12.33 MHz is the right clock, but it is not the right one according to nVidia’s analyses.

By the way, do you have any experience to implement audio TDM functions on nVidia platform? If yes, can you share the register settings for our reference? Thanks!

Best regards,

Sam Ting

  • 0
    TI__Expert 5645 points

    Hi Sam,

    As far as PCM186x TDM mode goes, the frame rate in TDM mode fixed to 256 BCK per frame, and the duty cycle of the LRCK (or frame sync signal) can be either a 50 / 50 duty cycle, or a single bit at the start of the frame. Hence, the BCK should have a frequency of 256×Fs. 

    As far as implementing TDM function on nVidia platform goes, unfortunately we do not have any expertise in that area. From PCM186x device configuration standpoint, we can definitely help you w. detailed register configuration if you need any furthur assistance. Please let us know if you need help in this front in the future. Of course, we will need to know more about the overall system and use case for complete PCM186x device configuration.

    Best regards,
    Ravi

  • 0 in reply to Ravi Patil
    Genius 4915 points

    Hi Ravi,

    There are some questions, pls help it.

    1. If PCM1864 is the master mode, that TDM duty cycle can't be 1/256,  right?

    2. You  meant BCLK is 256*fs, but I think should be SCL=256*fs? (MCLK=12.288MHz, BCLK=3.072MHz, LRCK=48KHz)

    3. Currently, the customer setting is PCM1864 is the slave, SCK=9.6MHz, BCLK=3.072MHz, LRCK=48KHz, seems can't get Dout, can I change the SCK=BCLK=3.072MHz and adjust the PLL?

    Appreciate your help!

  • 0 in reply to Jerry Chu
    Genius 4915 points

    Hi Ravi,

    I understand the BCLK should be 256*fs. So, I remove EVM R21 and BCLK to SCKI and change the PCM1864 PLL setting. After do that, seems everything is good, I can get CH4 data, but get some strange data after CH4. (I didn't use second ADC.) Can you help it?

    BTW, pls ignore last post. Thanks!

    CH3

    CH4

  • 0 in reply to Jerry Chu
    TI__Expert 5645 points

    Hi Jerry,

    Can you please share the config file you are running? Also, can you please outline the details of your test setup as well...this will allow me to configure the part for your requirements and make sure i can test the same on the EVM before sharing the config. Thanks.

    Best regards,

    Ravi

  • 0 in reply to Ravi Patil
    Genius 4915 points
    Hi Ravi,
    You can try the below setting. MCLK=BCLK=12.288MHz.

    w 94 20 02
    w 94 28 10
    w 94 20 42
    w 94 20 4a
    w 94 20 4e
    w 94 23 0f
    w 94 22 07
    w 94 28 11
    w 94 0b 4c
    w 94 0c 01
    w 94 0b 4f
  • 0 in reply to Jerry Chu
    TI__Expert 5645 points
    Thanks for sharing the configuration Jerry. I do see some register settings that need changes and am working on an EVM to get the right configuration. I'll share the working config as soon as I test and verify the same before sharing.

    Best regards,
    Ravi