This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3253: DC Offset and aliasing

Part Number: TLV320AIC3253

I am using Pure Path Studio to create a pass through program -- PDM input to I2S output. The ADC is set up with the MCLK at 4MHZ for a sample rate of 15.625 KHz. There is a 4x decimation block followed by an interprocessor block and ultimately into an 8x interpolator. The audio coming out of the I2S is at the correct sample rate but has a constant DC offset and has aliasing (eg. 9KHz sinusoidal stimulus is picked up as 7KHz). Any ideas what could be going wrong?

  • HI, Abhiray.

    From your description, it seems that the output is on the DAC, not on the I²S interface, can you confirm?. Can you share a screenshot of the processflow?. Is there any reason to have that specific sampling rate?, for that you should not expect to have any audio signal above 7.8125KHz. Can you share the clock settings you are using?, I wonder if the issue is also related to an incorrect clock configuration.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • I've attached a screenshot. My understanding is that the I2S output is via the DSP_D miniDSP as setup in the attached process flow. Am I misunderstanding how this works? 

    Our host processor's I2S bus in master mode can only supply an MCK of 4MHZ and a MCK/LRCK ratio of 256 which corresponds to 15.625KHz. We would like it to be exactly 16KHz if you have any ideas on how to make that possible?  

    The clock settings are as follows:

    MCLK= 4MHz

    PLL is setup to produce PLL_CLK = 96MHz

    NDAC = 2

    MDAC = 8

    DOSR = 384

    NADC divider powered off

    MADC = 24

    AOSR = 128

    Can you also explain the role of the decimator and the interpolator factors? Is the 4x decimation happening after PDM->PCM decimation/conversion? What is the Fs in section 2.3.4.3.1 in slau303 refer to? Is it the audio sample rate i.e 15625 Hz in our case or is it the oversample rate?

  • The aliasing issue is resolved. The problem was that the AIC was configured to provide an I2S LRCLK with twice the correct frequency (the AIC is configured as the master and the host processor the I2S slave).  

    However, there is still a large DC offset. Any ideas for the source for that?

  • Hi, Abhipray,

    A large DC offset should not be expected, but something to verify is to use a high pass filter on the PPS process flow to remove it. Can you please provide more details about the DC offset observed?, what is the amplitude and where are you measuring it is useful to identify the root cause. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Hi Diego,

    The DC offset could be explained by the PDM microphone producing a DC offset perhaps. 

    Going back to the aliasing issue, it turns out that it was actually not resolved. The way I was testing was by capturing audio samples while playing a sine sweep in Audacity. It turns out that the project sample rate was set to 16KHz so it wasn't playing the audio stimulus above 8KHz. When I set it back to the sample rate of the audio stimulus (44.1KHz), I am recording aliasing again. 

    Can you answer the following questions I had earlier that might be helpful?

    Can you also explain the role of the decimator and the interpolator factors? Is the 4x decimation happening after PDM->PCM decimation/conversion? What is the Fs in section 2.3.4.3.1 in slau303 refer to? Is it the audio sample rate i.e 15625 Hz in our case or is it the oversample rate?

    Could it have anything to do with the fact that reg [0][61] (ADC Signal Processing Block Control Register) is set to minDSP_A instead of one of the other processing blocks? In the datasheet, Table 8. ADC / Digital Microphone Processing Blocks shows that the decimation filters are available only for PRB_R* processing blocks.

    Thanks!

  • Hi, Abhipray,

    It is possible that the DC offset is related to the PDM mic, although it should not be an expected behavior of the mic.

    Regarding your questions,  the interpolation and decimation happens right before the miniDSP, after PDM data capture. Fs is the sapling rate of the codec.

    When the miniDSP is used, the decimation filters are configured with PPS by selecting the corresponding block, the table you mention is a summary of the features available on each processing block.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer