TAS6424-Q1: Does MCLK need to sync with FSYNC and SCLK?

Hi PY,

The MCLK does not need to be in phase with FSYNC and SCLK.  As long as the ratio is correct the device will not give you a clock error, e.g. FSYNC = 48kHz, SCLK = 3.072 MHz and MCLK = 12.288 MHz.

Best, Tuan

Hi Sir

The reason is we find the description on datasheet show as below. How

9.3.1.6 Audio-Clock Error Handling
When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts all
channels into the Hi-Z state.

Does there have any way to make sure ratio of MCLK-FSYNC or clock halt?

Hi Jimmy,

That is correct.  Ratio indicates that there are counters for MCLK, SCLK and FSYNC.  So as long as 4x SCLK = MCLK and 256X FSYNC = MCLK the device works.  This is edge triggered so MCLK does not have to be in phase.

Hope this helps.

Best, Tuan

Hello PY and Jimmy,

If the answers help you solve the issue, will you please kindly close this thread by clicking issue resolved.  If not, please let me know how I can be of assistance.

You can always start a new thread as issue arises.

Have a great weekend.

Hi

Issue still not closed now due to audio clock error bit still alarm.

MCLK=12.288MHz, SCLK=3.072MHz, FSYNC=48KHz

Does there have any extra timing informaiton or jitter of i2S clock or MCLK?

Regards

Hi Jimmy,

That's good that it works for you.  An inverter on MCLK may have worked in this case.

Will you please close out this thread if the issue is resolved.  Thank you.

Best, Tuan