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TLV320DAC32: Possible I2S Configuration Issue

Arthur Thompson27
Expert 1780 points
Part Number: TLV320DAC32
Other Parts Discussed in Thread: CC8520,

I have a CC8520 receiving wireless audio and sourcing I2S to a TLV320DAC32.  CC8520 is the I2S master.

I have a substantial amount of hiss in my TLV320DAC32 output.  Speech is intelligible but the hiss makes it not easy to hear.

 I took a screenshot of the I2S bus with some putty over the digital microphone.  This I2S waveform looks pretty quiet to me yet I hear the hiss.

 

TLV320DAC32_I2S_diff.txt 
#################################
###### I2S Input           ######
###### Left Differential   ######
#################################

## Device address: 0011000 
## 00110000 = 0x30

w 30 00 00 # Go to page 0
w 30 01 80 # SW reset
w 30 07 2A # Fsref = 48kHz, Left data->LDAC, Right data->RDAC, Dual Rate Mode
w 30 0E C0 # AC-coupled driver, stereo fully-diff output
w 30 25 80 # LDAC power up, RDAC power down, HPLCOM diff of HPLOUT
w 30 2B 0C # LDAC unmute, gain = -6dB
w 30 2C 80 # RDAC mute, gain = 0dB
w 30 2F 80 # LDAC routed to HPLOUT
w 30 33 0D # HPLOUT unmute, fully powered up, 0dB
w 30 3A 0D # HPLCOM unmute, fully powered up, 0dB
w 30 40 00 # RDAC not routed to HPROUT
w 30 41 04 # HPROUT mute, not fully powered up, 0dB
w 30 48 04 # HPRCOM mute, not fully powered up, 0dB
w 30 65 01 # DAC_CLKIN = CLKDIV_OUT (not using PLL)

w 30 09 00 #  FIXES I2S, DON'T UNDERSTAND
If I mute the DAC_L input to the HPLOUT, the hiss goes away (as well as all any sound from the mic).

 

So I think the problem is one of these 3 things

1.       Real analog noise on the microphone CC8520 source

2.       Real analog noise on the receiver CC8520 sink

3.       An artifact of incorrect DAC32 configuration

 

I feel like #3 is the most likely because I’ve tested source and sink together as a system feeding the LINER input of the DAC and that whole system is free of noise.  And I’m not sure I understand how to configure I2S.

 

Thanks,

Arthur

  • 0
    TI__Guru** 102135 points
    Hi Arthur,

    In the script you attached I noticed there is a command at the end. The note on the side means that when you perform that command the hiss is removed? or what does it mean?
    Also have you tried to change w 30 07 2A to w 30 07 0A?

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • 0 in reply to Ivan Salazar
    Expert 1780 points

    Hi Ivan,

    The last w 30 09 00 command was necessary to get I2S working.  I wasn't sure why register 09 would sometimes get set to 0x0F after I ran the script.  But setting it back to 0x00 again gives me audio, though it still has the hiss.

    I set that register 7 Dual Rate mode back when I was playing around with settings to get I2S working, and forgot to change it back.  Switching to 0A has no effect on the hiss I'm hearing though.

    Thanks,

    Arthur

  • 0 in reply to Arthur Thompson27
    Expert 1780 points

    Hi Ivan,

    I found some settings in the GUI that work to give me clean audio.  I had to use the PLL (you noticed before I was using a DAC_CLK source from the CLKDIV_OUT).

    Here is a screenshot of the settings I used to get rid of the hiss.

    With this information can you figure out how I can get this working without the PLL?

    I'm also attaching a register map that corresponds to the working settings.

    DAC32 Register Map Page 0 1256 02Aug.xls

    DAC32 Register Map Page 1 1256 02Aug.xls

    Thanks,

    Arthur

  • 0 in reply to Arthur Thompson27
    Expert 1780 points

    Bumping this thread because I'm trying to figure out if this configuration can work without the PLL.

    Thanks,

    Arthur

  • 0 in reply to Arthur Thompson27
    TI__Guru** 102135 points
    Arthur,

    The clock signal at DAC_CLK should be 256*Fs, for this application Fs = 48kHz so DAC_CLK should be 12.288MHz.
    If your MCLK is 12.288MHz then it should also work if not using the PLL, this is odd.
    Also from the PLL settings you used you're basically setting the same output frequency as the input, which is 12.288MHz.
    Perhaps your MCLK is somewhat noisy/unstable and PLL is working on providing a more stable clock? Do you have captures of your MCLK signal?

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators