(I hope there are still people around at TI who can answer this question!)
I have a converter board built up and I am testing it. DIT side works fine.
On the receive side, the device is configured to use any of the RX inputs into the DIR, which feeds the SRC, which feeds audio port A. Audio port A is a master which feeds a DAC as a slave.
The DIR, SRC and Audio Port A all use RXCKI as their reference clock. RXCKI is driven by a 24.576 MHz oscillator (which also drives the DAC's MCLK input).
When connected to an S/PDIF or TOSLINK source with a sample rate of 48 kHz or 96 kHz, the DIR locks, RXCKO (enabled for monitor purposes but otherwise not used) toggles at a solid 12.2880 MHz and I get audio.
When the source sample rate is changed to 44.1 kHz or 88.2 kHz, the DIR does not lock (LOCK goes high). RXCKO outputs an ~11.43 MHz clock that is not very stable.
Nothing in the documentation indicates that this configuration should not work.
At initialization, I set register 0x0D is set to 0x00; bit 3 sets the reference clock to RXCKI, and during operation I will reload this register if the user selects another input source. Bit 3 is always 0, though.
Register 0x0E is set to 0x11, to let the PLL2 output clock drive RXCKO and to not stop it when the receiver is not locked. (If set to 0x01, RXCKO stops shortly after switching to the 44.1/88.2 rates.)
Register 0x0F is set to 0x21, registers 0x10 and 0x11 are set to zero, which set the receiver PLL1 P, J and D constants to 2, 8 and 0, respectively, per table 4 in the data sheet.
What am I doing wrong? Where should I look?