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PCM1792A: what might cause false values to be read via I2S?

Vincenzo Pizzolante
Mastermind 25656 points
Part Number: PCM1792A


hi

We have some strange behavior and we wish to ask about the digital inputs hysteresis, specifically for the I2S clicks and data.

what's the amplitude of a glitch that can cause a false value to be read?

any advices/guidelins on how to improve the noise immunity of PCM1792A?

thanks a lot in advance

KR

Vincenzo

  • 0
    TI__Guru 54323 points
    I am not sure of the amplitude that might cause a mis-read, as it is unspecified. In general, I would recommend a small series resistor on the I2S lines to help with noise immunity (10-22 ohm). I would also recommend that care be taken to not route other high power switching signals by the I2S lines.

    Let me know if that helps or if you have some data showing the glitches.

    Thanks!
    Paul
  • 0 in reply to Paul_Frost
    TI__Mastermind 25656 points

    hi Paul,

    Currently we can not add any serial resistor in the I2S lines because we don't have  access to the customer's devices.

    I am more looking for more information on the relation between the I2S clocks --LRCK+BCK+MCLK -- :

    - is there a timing diagram that show any condition in between the three.

    - from the datasheet I can't see any MCLK relation with the other two clocks

    To confirm the issue: we believe inside the dac there is a shift-register. Do we know how the dac sees the bit clock as rising edge in terms of timing

    and levels?

    I attached a sketch where the 1st wave is something similar to what we have. The 2nd wave is what we believe how the DAC seeing the BCK.

    Is it correct?

    thanks a lot in advance

    KR

    Vincenzo

  • 0 in reply to Vincenzo Pizzolante
    TI__Guru 54323 points

    Hi Vincenzo,

    Figure 27 shows the relationship between LRCK, DATA, and BCK.  The only requirement for SCLK is that is synchronized with LRCK, but there is no phase requirement.  I recommend SCK and LRCK are derived from the same source.

    In regards to the glitch on BCK, it is possible the edge is misread if the glitch is near the VIL/VIH levels of the device.  It would be good to try to reduce the reflections on the line.

    Thanks!

    Paul