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SRC4382: SRC4392 Signal Path

Holly Gu
Intellectual 2750 points
Part Number: SRC4382

Hi Team,   

    I would like to check with you, could we forward the signals coming from the DIR inputs and Port A I2S  directly to Port B without passing through the ASRC, as below,

    Another question is, if the sample frequency of PortA and DIR changes, how to tell PortB(Master mode) change its MCLK and LRCLK accordingly to keep input/output sample frequency the same? Seems SRC4382 can't get real time sample frequency of PortA and DIR. 

  • 0
    TI__Expert 5645 points
    Hi Holly,
    SRC4382 can be configured such that the digital input at Port A can be routed to Port B. The audio serial ports are configured using control registers 0x03 through 0x06.

    Similarly, we can also configure the output of DIR to be routed to Port B as outlined in the above diagram.

    As far as DIR output to Port B routing is concerned, when operating in MASTER MODE, SRC4382 allows the serial ports to derive the LRCK and BCK output from the selected MCK source which can be MCLK, RXCKI or RXCKO. To enable the Port B to change the sampling freq, I would recommend to use DIR recovered clock output [RXCKO] as master clock for Port B.

    Hope this clarifies your questions. Thanks.

    Best regards,
    Ravi
  • 0 in reply to Ravi Patil
    TI__Intellectual 2750 points

    Hi Ravi,

      The key problem is the sample frequency of PORTB should be exactly the same as input DIR/PORTA, how can SRC4382 know the PortA/DIR sample frequency change and adjust accordingly?

  • 0 in reply to Holly Gu
    TI__Intellectual 2750 points
    Hi Team,

    Any update for this question? Thanks.
  • 0 in reply to Holly Gu
    Genius 3945 points

    "Any update for this question? Thanks."

    The support staff (Ravi?) for these parts has gone AWOL. I'm still waiting for an answer to my question. It's been a month.

  • 0 in reply to Holly Gu
    TI__Expert 5645 points

    Hi Holly.

    As far as the DIR block in SRC4382 goes, it has mainly TWO functions - AES3 decoding and clock recovery. DIR can be configured to output the recovered MASTER CLOCK output (RXCKO). The RXCKO clock can be routed internally to other function blocks, where it may be further divided to create left/right word and bit clocks. So when the input sampling rate on the DIR changes, the Port B would know the change if the Audio Serial Port B is configured to use RXCKO as the  Master clock source & DIR as data source as highlighted below.

    Hope this clarifies things wrt frequency change. NOTE that if the sampling rate is subject to change on the fly, it may have some audible artifacts...Thanks.

    Best regards,

    Ravi

  • 0 in reply to Ravi Patil
    TI__Intellectual 2750 points

    Hi Ravi,

     

       How about when input is PORT A, how can PORT B sync with PORT A? Customer should configure BDIV[1:0], right?