Linux/TAS2553: Audio does not proper.

Hi Nikunj,

Do you know if there is no output all? Or is there sound but is not correct?
Could you please share some captures of the related signals? Like speaker outputs, BCLK, WCLK and DIN. I would like to verify if the outputs are enabled and switching, and also verify the clock signal frequencies.
Could you please share the clock frequencies as well as the sampling frequency? It would be best to know the actual values that are being sent to the device for configuration.
Have you verified your commands by reading back the registers from TAS2553?
I can help you with the TAS2553 configuration by its registers based on the application, although I cannot support the driver commands. The TAS2552 driver is provided as an example and tool, but I cannot support it.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi Ivan;

Thanks for your quick reply.

Do you know if there is no output all? Or is there sound but is not correct?

Ans: We got sound but does not proper.

Please find the below signals:

1) MCLK

2) WCLK: (Frequency : 92.165 Khz)

3) BITCLK [Frequency: 2.90 Mhz]

4) Signal at speaker (-Ve) terminal

Could you please share the clock frequencies as well as the sampling frequency?

Ans: clock frequency means MCLK so we give it 12 Mhz. Also we are not passing any sampling frequency in our configuration.

Have you verified your commands by reading back the registers from TAS2553?

Ans: No

Also tell who can help us for the Linux driver support for TAS2553 Codec IC?

Thanks & Best Regards;
Nikunj Patel

Nikunj,

Sampling frequency for TAS2553 should match with WCLK frequency. This is explained in datasheet section 7.3.7 on page 16. It is usually 44.1kHz or 48kHz.
Also as WCLK is 1 bit long so the device must be configured for DSP mode (more details on datasheet page 25).
Usually BCLK and WCLK are multiples (related in frequency) e.g. for WCLK = 48kHz and 32bit data, BCLK should be 3.072MHz (48kHz*32bit*2channel). Is BCLK supposed to be 32 times WCLK frequency?

The device should be configured to work properly.
- Clock tree as explained in section 7.3.7. Related registers: 0x01, 0x08, 0x09, 0x0a
- Data format as explained in section 7.4.1. Related registers: 0x03, 0x05
- Device configuration as explained in section 7.5.4, register 0x02

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi Ivan;

We are giving the sampling frequency(44.1kHz or 48kHz.) which is manage by the aplay Application.

Is BCLK supposed to be 32 times WCLK frequency?

Ans: As per our manual measuring the BCLK=2.90 MHz and WCLK=92.165 KHz and as per those BCLK is 32 times to the WCLK. (92.165 Khz x 32 = 2.94928 Mhz)

So, Please tell us where we are wrong?

Can TAS2553 is compatible with internal OC? because I have enable the internal OC by the below method but still audio is not correct.

pll_clkin = 1800000;

pll_sel = (TAS2552_PLL_CLKIN_1_8_FIXED << 3) & TAS2552_PLL_SRC_MASK;

snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_PLL_SRC_MASK,pll_sel);

Thanks & Best regards;

Nikunj Patel

Gentle reminder;

Thanks & Best Regards;
Nikunj Patel

Nikunj,

If you're giving 44.1kHz or 48kHz by aplay command, then WCLK signal should be 48kHz, not 92.165kHz.
I would start looking at that to obtain correct signals from the host.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

HI Ivan;
can you suggest me the next steps for more debugging for above issue?

Thanks & Best Regards;
Nikunj Patel

Hi Ivan;
I have read all the registers of TAS2553 IC. please check the below value of each registers

[ 2065.141544] TAS2552_DEVICE_STATUS =0x00
[ 2065.149087] TAS2552_CFG_1 =0x36
[ 2065.156089] TAS2552_CFG_2 =0x6d
[ 2065.162707] TAS2552_CFG_3 =0x5d
[ 2065.168523] TAS2552_DOUT =0x00
[ 2065.175402] TAS2552_SER_CTRL_1 =0xc4
[ 2065.182972] TAS2552_SER_CTRL_2 =0x00
[ 2065.189736] TAS2552_OUTPUT_DATA =0xc8
[ 2065.197733] TAS2552_PLL_CTRL_1 =0x19
[ 2065.205240] TAS2552_PLL_CTRL_2 =0x03
[ 2065.212678] TAS2552_PLL_CTRL_3 =0x6f
[ 2065.219696] TAS2552_BTIP =0x8f
[ 2065.226314] TAS2552_BTS_CTRL =0x80
[ 2065.233463] TAS2552_RESERVED_0D =0xbe
[ 2065.240566] TAS2552_LIMIT_RATE_HYS =0x08
[ 2065.249108] TAS2552_LIMIT_RELEASE =0x04
[ 2065.257149] TAS2552_LIMIT_INT_COUNT =0x00
[ 2065.265606] TAS2552_PDM_CFG =0x01
[ 2065.272442] TAS2552_PGA_GAIN =0x10
[ 2065.279033] TAS2552_EDGE_RATE_CTRL =0x40
[ 2065.287557] TAS2552_BOOST_APT_CTRL =0x0f
[ 2065.295669] TAS2552_VER_NUM =0x08
[ 2065.302443] TAS2552_VBAT_DATA =0x00

So please check that and tell us is there any wrong happen to there. because i have doubts on "TAS2552_SER_CTRL_1", "TAS2552_CFG_1" resistors.

Thanks & Best Regards;
Nikunj Patel

Hi Nikunj,

The settings for the mentioned registers does not seem to be correct.
CFG_1 (register 0x01) is selecting internal 1.8-MHz oscillator as source for PLL, that can be correct, but it also sets Class-D to Mute and sets the device into Software Shutdown mode. That is not correct.
SER_CTRL_1 (register 0x05) sets BCLK and WCLK as output, so the device is set as Master for digital interface, and the data format is set to DSP. Both things are not correct. This register value explains why WCLK is 1-bit long (DSP format).

Do you know how is the device being initialized? Perhaps if you can edit the initialization to the correct values the audio will be good.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi Ivan;
Thanks for your quick reply.
Sorry for inconvenience. I am out of office for two days so I will check another setting and reply back after two days.

Thanks & Best regards;
Nikunj Patel

Hi Ivan;

We changed the dtsi configuration files as below; in which we select the CPU as master and communication mode is I2S.

sound0: sound0 {

status = "okay";

               compatible = "simple-audio-card";

               model = "ti-tas2550";

               simple-audio-card,name = "TAS2552";

               simple-audio-card,format = "i2s";

               /*simple-audio-card,mclk-fs = <256>;*/

               simple-audio-card,widgets =

"Speaker", "Speaker External",

"Line", "In";

               simple-audio-card,routing =

                                "Speaker External", "OUT",

                                "In", "DAC";

               simple-audio-card,cpu {

                       sound-dai = <&mcasp3>;

               };

               simple-audio-card,codec {

                       sound-dai = <&tas2552>;

                       system-clock-frequency = <1800000>;

                       system-clock-id = <TAS2552_PLL_CLKIN_1_8_FIXED>;

               };

       };

Please check the below register dump valies when we have played the 48000 Hz wav file then wav file

During this my WLCK frequency was 12KHz and BCLK frequency was 370KHz.

 

Playing WAVE '/usr/bin/piano2.wav'
Signed 16 bit Little Endian, Rate 48000 Hz, Stereo


[  200.325124] TAS2552_DEVICE_STATUS    =0x20
[  200.332962] TAS2552_CFG_1    =0x34
[  200.339033] TAS2552_CFG_2    =0xec
[  200.346000] TAS2552_CFG_3    =0x5d
[  200.352423] TAS2552_DOUT     =0x00
[  200.358407] TAS2552_SER_CTRL_1       =0x00
[  200.366342] TAS2552_SER_CTRL_2       =0x00
[  200.374276] TAS2552_OUTPUT_DATA      =0xc8
[  200.381671] TAS2552_PLL_CTRL_1       =0x1b
[  200.388690] TAS2552_PLL_CTRL_2       =0x0b
[  200.396614] TAS2552_PLL_CTRL_3       =0xf9
[  200.403978] TAS2552_BTIP     =0x8f
[  200.409963] TAS2552_BTS_CTRL =0x80
[  200.417823] TAS2552_RESERVED_0D      =0xc0
[  200.425436] TAS2552_LIMIT_RATE_HYS   =0x28
[  200.433447] TAS2552_LIMIT_RELEASE    =0x04
[  200.441406] TAS2552_LIMIT_INT_COUNT  =0x00
[  200.449379] TAS2552_PDM_CFG  =0x01
[  200.456525] TAS2552_PGA_GAIN =0x10
[  200.463696] TAS2552_EDGE_RATE_CTRL   =0x40
[  200.471645] TAS2552_BOOST_APT_CTRL   =0x0f
[  200.479526] TAS2552_VER_NUM  =0x08
[  200.486709] TAS2552_VBAT_DATA        =0x00

Thanks & Best Regards;

Nikunj Patel

Hi Ivan;
can you please help us to solved this issue.

Thanks & best Regards;
Nikunj Patel

Nikunj,

The most important things to consider are clock settings and internal block settings which is almost the first half of the registers you shared above.
I reviewed these and found the following:
- TAS2552_CFG_1 =0x34 // The SWS is not enabled but it seems that the Class-D is still muted.
- TAS2552_SER_CTRL_1 =0x00 // This looks good now, it sets WCLK and BCLK as input (slave mode), selects I2S format and 16bit data.
- The rest of the CFG and SER_CTRL values seem to be good.
- PLL_CTRL // From the values above I identified P = 0, J = 27, D = 3995. If Fs is 48kHz then the output of PLL should be 24.576MHz. I would recommend to do some minor changes to PLL values as P = 0, J = 27 and D = 3067. This would give 24.576030MHz at the output of PLL.

However, the one thing that I don't understand so far is why your WCLK is 12kHz and BCLK is 370kHz. These are not correct, and these signals should be coming from the host processor in your system (because TAS2553 is set as slave).

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi Ivan;

Thanks for your reply;

TAS2552_CFG_1 =0x34 // The SWS is not enabled but it seems that the Class-D is still muted.

Ans: We have changed it to 0x30 but still no any effect.

However, the one thing that I don't understand so far is why your WCLK is 12kHz and BCLK is 370kHz. These are not correct, and these signals should be coming from the host processor in your system (because TAS2553 is set as slave).

Ans: can we use TAS2553 as Master?

if yes what should be the WCLK and BCLK frequency value generate by TAS2553 if we don't provide the MCK(because we used the 1.8 MHz internal Oscillator)

Note: We only use DIN pin of TAS2553 and 8 Ohm Speaker as output.

Thanks & Best Regards;

Nikunj Patel