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TAS5825M: What fault events will cause this Smart Amp to turn off / shutdown and what is the method to clear the different fault events?

John Pierson
Intellectual 320 points
Part Number: TAS5825M
Other Parts Discussed in Thread: PUREPATH-CMBEVM,

Hello,

I am trying to determine from the TAS5825M datasheet, what fault events will cause the output of the amplifier to turn off or shut-down. I believe the following conditions may cause the amp output to shut-off or shut-down:

CHAN_FAULT Register (Offset = 70h) [reset = 0x00]

CH1_DC_1 left channel DC fault, CH2_DC_1 right channel DC fault

GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]

DVDD_UV_I DVDD UV fault, DVDD_OV_I DVDD OV fault

PVDD_OV_I PVDD OV fault, PVDD_UV_I PVDD UV fault

GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]

CBC_FAULT_CH2_I right channel cycle by cycle over current fault, CBC_FAULT_CH1_I left channel cycle by cycle over current fault

OTSD_I over temperature shut down fault

I am looking specifically for what events can cause the output audio to interrupt momentarily or to shut-off or shut-down.

Thank you and kind regards,

John

PVDD OV fault, PVDD UV fault

DVDD OV fault, DVDD UV fault

OTSD_I Over Temperature Shutdown fault

  • 0
    TI__Guru 52115 points

    Hi John,

    Basically, the following events can cause TAS5825M to shut down.

    a) DC fault

    b) OC fault

    c) CBC fault

    d) PVDD OV fault

    e) PVDD UV fault

    h) Clock fault

    g) OT fault

    Thanks.

  • 0 in reply to Andy Liu (BMS)
    Intellectual 320 points

    Hi Andy,

    Thank you for this list of events that can shut down the TAS5825M Smart Amp. I have a couple of questions regarding this:

    1.) Which Events can be cleared by I2C writes to a TAS5825M register?

    2.) Which Events require a power cycle to clear the fault condition?

    Thank you,

    John Pierson

  • 0 in reply to John Pierson
    TI__Guru 52115 points
    Hi John,

    None of these faults requires power cycling.

    As far as I know, the TAS5825M device can recover automatically, if the fault conditions for Clock fault, PVDD UV fault or PVDD OV fault no longer exist.

    You can write to the FAULT_CLEAR Register to clear the fault for other types of faults.

    Andy
  • 0 in reply to Andy Liu (BMS)
    Intellectual 320 points
    HI Andy,

    I really appreciate your help with my questions! If it is OK with you, I would like to look closer at each fault condition in further detail. I think it would make sense to focus on one fault type at a time. I would first like to investigate what conditions can cause a Clock Fault. From page 28 in the TAS582M data sheet:

    "When any kind of clock error, Out of Range, SCLK-FSYNC Ratio, or Clock halt is detected, the device puts all
    channels into the Hi-Z state and report Clock Error in Register 113 (Register Address 0x71). When all audio
    clocks are within the expected ranges, the device automatically returns to the state it was in, but the clock error
    flag in register 113 need to cleared by Register 120 (Register Address 0x78) manually ."

    We are seeing Clock Fault conditions when using the PUREPATH-CMBEVM Rev D, PCB No. AIP006G along with the TAS5825MEVM Rev D, PCB No. AMPS023A. When this happens, I use the PPCM Register Map tool and see that the Global Fault 1 register (Address 0x71), bit-2 = 1. This indicates a Clock Fault. We see this sometimes on power up or when it is being used. This issue exists when using USB audio input and when using the Analog Input path.

    What conditions should we be looking for that might be causing this fault?

    Should we continue this discussion in this E3E case, or should I submit a separate E2E support request for this issue?

    Thank you for your help.
    Regards,
    John Pierson
  • 0 in reply to John Pierson
    TI__Guru 52115 points

    Hi John,

    Do you use the PPC3 to initialize the TAS5825M device? I don't see any fault detected in the PPC3 GUI.

    Usually, when the TAS5825M goes into the play mode, its clock monitoring circuitry will start to monitor the incoming clocks. If one or more of the following errors occurs, the clock fault will be reported in the Register 0x71.

    1) Non-Supported SCLK to LRCK Ratio
    2) Non-Supported LRCK rate
    3) SCLK or LRCK has stopped

    You can remove this clock fault by writing to the Register 0x78. However, if the fault condition continues, the same fault will be reported again.

    Andy

  • 0 in reply to Andy Liu (BMS)
    TI__Guru 52115 points
    Hi John,

    If the I2S clocks become normal again after the clock fault occurs, TAS5825M will recover automatically and no action is required.

    However, the clock fault bit in Register 0x71 is a sticky bit by default. It will not go away even after the clocks become normal. To clear it, write 0x80 to the Register 0x78.

    Andy
  • 0 in reply to Andy Liu (BMS)
    TI__Guru 52115 points
    TAS5825M will NOT recover automatically if the any of following faults occurs.

    a) DC fault

    b) OC fault

    c) CBC fault

    d) OT fault

    You have to write 0x80 to the Register 0x78 to clear the fault and TAS5825M will then try to recover. However, if the fault condition continues, the same fault will be reported and TAS5825M will shut down itself again.
  • 0 in reply to Andy Liu (BMS)
    Intellectual 320 points
    Hi Andy,
    I have found that I now have a .ppc3 configuration file that I created that uses the USB interface for audio out - into the PPCM and then into the TAS5825M EVM. It reliably establishes an audio stream from the PC to the TAS5825M. So this aspect of my questions in this case can be considered to be resolved. I will reserve stating that this case is fully resolved until we address the other fault condition questions I have asked about.
  • 0 in reply to Andy Liu (BMS)
    Intellectual 320 points
    Hi Andy,
    This explains why I see the Clock Fault bit set in Register 0x71. I now understand this is 'sticky" and requires a write to the Fault Clear register 0x87. Thank you for your explanation of this.
  • 0 in reply to Andy Liu (BMS)
    Intellectual 320 points
    Hi Andy,
    This is the important information I have been looking for. I need to insure I understand each of these faults as follows:

    a) DC Fault - Datasheet section: 9.5.3.3.3 DC Detect - This is clear. Until the detected DC offset is cleared, writes to register 0x78 will not clear this fault.

    b) OC Fault - Datasheet section: 9.5.3.3.2 Overcurrent Shutdown (OCSD) - My understanding is the OCE thres (Over-current Error Threshold) is 7.5 Amps typ. This will is shut the affected channel down / off. Writes to register 0x78 will not clear this until the fault is cleared.

    c) CBC Fault - Datasheet section: 9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
    This fault I don't understand. From the datasheet:

    "The CBC current-limiting circuit terminates each PWM pulse limit the output current flow to the average current
    limit (ILIM) threshold. The overall effect on the audio in the case of a current overload is quite similar a voltageclipping
    event, temporarily limiting power at the peaks of the music signal and normal operation continues without
    disruption on removal of the overload."

    OCE thres Over-Current cycle-by-cycle limit = 6.5 Amps typ

    My understanding from the description above is this will NOT shut down / off the affected channel. It will affect the audio. But it will not require a write to register 0x78 to clear this.

    Is this correct?

    On the other hand, I see Table 55. GLOBAL_FAULT2 Register Field Descriptions:
    CBC_FAULT_CH2_I right channel cycle by cycle over current fault
    CBC_FAULT_CH1_I left channel cycle by cycle over current fault
    So this now looks like a fault that must be cleared... Is this correct?

    Important question: From an over current protection perspective does this imply that we MUST keep peak currents to <6 Amp pk-pk to safely operate the TAS5825M from shutting down / off due to overcurrent?


    d) OT Fault - OTE Thres Over Temperature Error Threshold = 160 C (typ). I understand that this fault cannot be cleared until the OTE error threshold goes away - once the amplifier has sufficiently cooled down.

    Item c) - Is what needs clarification

    Thank you Andy for all your help with this!

    John
  • 0 in reply to Andy Liu (BMS)
    Intellectual 320 points
    Waiting for other questions to be resolved before this case can be closed
  • 0 in reply to Andy Liu (BMS)
    Intellectual 320 points
    See my post below for specific questions on the above response.
  • 0 in reply to John Pierson
    TI__Guru 52115 points

    Hi John,

    To make life easier for us, could you post your new questions in another e2e thread?

    Andy