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TLV320ADC3101: Asking for ADC3101 input source format

SHH
Mastermind 32316 points
Part Number: TLV320ADC3101


Hi team,

Customer uses ADC3101 on the IBI8 platform.

Here is the MCLK, BCLK, WCLK and DOUT waveform.

Would you please review the waveform to see any abnormal?

BR,

SHH

  • 0
    TI__Guru 57800 points

    Hi, SHH,

    The waveform shared actually seems to be in TDM/DSP format, not I²S, so the parameters of the table you are sharing are not applicable; please look to table 8.10. The waveform seems fine, but the only thing which should be double-checked is the ADC Data out, which seems to have an offset of half bit clock cycle, which may be a result of the Bit clock polarity used. Please review Page 0: Register 2 and let me know if you see any change in the output after changing the value of bit D3.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    TI__Mastermind 32316 points
    Hi Diego,
    P0R2 D3 definitions seem not show in the datasheet.
    Could you please provide this register setting for us?

    BR,
    SHH
  • 0 in reply to SHH
    TI__Guru 57800 points

    Hi, Shh,

    Page 0: Register 2 is reserved, but I see the issue, there is a typo on my response, where the correct register to change the polarity of the bit clock is Page 0: Register 29.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer