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PCM9211: Configure PCM9211 ADC as I2S master via MPIO_C

Jesper Jensen58
Prodigy 50 points
Part Number: PCM9211

Hi.

I need help to configure the PCM9211 internal ADC as I2S master.

My intention is to set the ADC in standalone mode, and then as I2S master, to let the device output 24-bit I2S to my DSP, which is in slave mode.

However, I can't get the MPIO_C pins to output anything.

The PCM9211 is sourced by a 24.576Mhz crystal. I want the output to operate with LRCLK = 96 kHz and BCLK = 6.144 MHz.

My current configuration is as follows

(script style from CodecControl SW)

##############################

# Reset the registers to default

w 80 40 00

w 80 40 33

w 80 40 C0

# Set the XTI Clock settings to SCK = XTI/1 = 24.576 MHz, BCLK = XTI/4 = 6.144 MHz and LRCLK = XTI/256 = 96 kHz

w 80 31 05

# Set MPIOC as ADC Standalone Mode

w 80 6F 41

# Set the ADC as I2S master, 256fs, with output format = 24-bit I2S

w 80 48 20

##############################

Any help is appreciated.

Thanks in advance.

Regards, Jesper Thoerring Jensen

  • 0
    TI__Expert 5645 points
    Hi Jesper,
    Welcome to e2e forum.

    Thanks for providing the detailed configuration along w the problem statement. I will evaluate the config and also recreate the routing requested and will provide the feedback once I test the same on my bench.

    Thanks & Best regards,
    Ravi
  • 0 in reply to Ravi Patil
    Prodigy 50 points
    Hi Ravi.

    Thank you for taking your time to help me resolve this issue.
    Do you have any findings yet?

    Best regards,
    Jesper Thoerring Jensen
  • 0 in reply to Jesper Jensen58
    TI__Expert 5645 points
    Hi Jesper,
    I did review your script/device configuration. The only changes/addition I would recommend is as follows -

    please configure the register value 0x48 to 0x40
    w 80 48 40

    And also, can you please configure the clock source to XTI by setting the register 0x42 to 0x02
    w 80 42 02

    Also, are you testing this on our EVM or your board? I plan to check the same on the bench on Monday. Thanks.

    Best regards,
    Ravi
  • 0 in reply to Ravi Patil
    Prodigy 50 points

    Hi Ravi.

    Thank for your suggestions.

    Unfortunately, this did not solve the issue.

    However, I am trying this on both my own board and on the EVM board.

    When I try it on the EVM board, I do see some changes, when monitoring the LRCLK (MPIOC_2), but not exactly what I expected.

    First of all, directly after reset, the LRCLK is running with 44.1 kHz - do you know where this comes from?

    When I program the EVM board, I can see that the LRCLK i somehow modulated, as if two clock sources are interfering with one another.

    So it seems to work, but I need to disable the 44.1 kHz source first. Do you know how I can do that?

    On my own board, the entire MPIO_C port is just left floating (I am using a PCB from another project, where the PCM9211 is used, but the ADC and MPIO_C port are unused).

    Should I use any pull-up or pull-down resistor for the port to operate correctly?

    The behavior of the port is as explained earlier - it is not doing anything at all.

    Again, thanks for taking your time helping me resolve this issue.

    Best regards,

    Jesper Thoerring Jensen

  • 0 in reply to Ravi Patil
    Prodigy 50 points
    Hi Ravi. Did you have time to look through my last question?
  • 0
    Prodigy 50 points

    So, I managed to find the solution to my problem, myself.

     

    It seems that the ADC in standalone operation set in master mode cannot be sourced from the XTI. If I set the ADC clock source to AUXIN1, and then feed this pin with a 24.576 Mhz clock, everything seems to work.

    Note that the EVM board has to be modified in order to make the ADC run as master. This is because of the TAS1020 I2S output which is connected to the MPIO_C port. So to make the ADC run as I2S master, the 4 connections to the TAS1020 have to be cut (easily done by cutting the lanes at U3 pin4, TP4, TP5 and TP6)

     

    This should be highlighted more clearly in datasheet. In revision B of the datasheet page 24 it say:
    "By running the ADC in Master mode, the ADC can operate from an external SCK source (such as a DSP or PLL circuit), and provide BCK and LRCK to the rest of the PCM9211 circuitry and external components."

    I think it should have said:
    "By running the ADC in Master mode, the ADC must operate from an external SCK source (such as a DSP or PLL circuit), and provide BCK and LRCK to the rest of the PCM9211 circuitry and external components."

     

    So, just to clear things out.
    The correct configuration is as follows:

    w 80 6F 41 (To set GPIO_C as ADC standalone mode)
    w 80 48 40 (To set ADC in I2S master mode, 512 fs)
    w 80 42 04 (to set ADC clock source to AUXIN1 (MPIO_C0 - Pin7) which is sourced by an external 24.576 MHz clock)