CCS/TLV320AIC3254: TLV320AIC3254 setting offset and bit clock question

Lawrence He

Part Number: TLV320AIC3254
Other Parts Discussed in Thread: LM49350, TLV320AIC3204, TLV320AIC3104

Tool/software: Code Composer Studio

Dear,

our client function block

We find the TLV320AIC3254 application reference guide about offset and bit clock, is could possible playback and record to setting default and inverter at the same time?

our client measurement 3G module I2S waveform as below chart: , it need our code device to setting inverter, but setting inverter, MIC to EVM go through Cell phone speaker will no sound.

Command line as below text,file.

Fullscreen 3254 V01.txt Download

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Clock Settings
# ---------------------------------------------
# The codec receives: 
# BLCK = 1.536MHz, WCLK = 48 kHz
###############################################
#
# Select Page 0
w 30 00 00
w 30 04 07
w 30 05 92
w 30 06 1C
w 30 07 00 00
w 30 0C 81
w 30 0B 8E
w 30 12 8E
w 30 13 81
w 30 1D 08
# INVERTER BCLK
###############################################



###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# Set the ADC Mode to PRB_P1
w 30 3d 01
#
###############################################



###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Select ADC PTM_R4
w 30 3d 00
#
# Set the input powerup time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# Recording Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# Powerup MIC BIAS
w 30 33 40
#
# Route IN3L to LEFT_P with 10K input impedance
w 30 34 04
#
# Route IN3R to LEFT_M with 10K input impedance
w 30 36 04
#
# Route IN3L to LEFT_P with 10K input impedance
w 30 39 04
#
# Route IN3R to LEFT_M with 10K input impedance
w 30 37 04
# Unmute Left MICPGA 24DB
w 30 3b 30
#
# Unmute Right MICPGA 24DB
w 30 3c 30
#
# Select Page 0
w 30 00 00
#
# Power up LADC/RADC
w 30 51 c0
#
# Unmute LADC/RADC
w 30 52 00
#
###############################################

#
# High Performance Stereo Playback
# ---------------------------------------------







###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# Set the DAC Mode to PRB_P8
w 30 3c 08
#
###############################################



###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the input powerup time to 3.1ms (for ADC)
# w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# Playback Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop
w 30 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Route LDAC/RDAC to LOL/LOR
w 30 0e 08 08
#
# Power up HPL/HPR and LOL/LOR drivers
w 30 09 3C
#

#
# Unmute LOL/LOR driver, 6dB Gain
w 30 12 06 06
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################

If any suggestion, Please advise me.

Thanks,

Best regards,

Lawrence.

over 7 years ago

0 Steve-Wilson over 7 years ago

TI__Mastermind 30240 points

Lawrence,

No this is not possible in the TLV320AIC3254. The Polarity is common for both S_DIN and S_DOUT.

best regards,
-Steve Wilson

0 Eric Lo72350 over 7 years ago in reply to Steve-Wilson

TI__Intellectual 915 points

Hi Steven

any solution for this application?

Eric Lo

0 Steve-Wilson over 7 years ago in reply to Eric Lo72350

TI__Mastermind 30240 points

Hi Eric,

Can you change the settings on the 3G module so that the DIN and DOUT use the same polarity?
best regards,
-Steve Wilson

0 Eric Lo72350 over 7 years ago in reply to Steve-Wilson

TI__Intellectual 915 points

Hi Steven
I don't know, need customer to check with the 3G modem vendor.
The story is below,

My customer original design was follow Airprime's ref desihn (3G moduel:MC8090 + TLV320AIC1106PW) and without any problem.
Now Airprime will phase out MC8090 and ask them to change to 3G module:WP8548 + TLV320AIC1106PW but they meet the noise issue.

I post this issue to E2E before and the answer is TLV320AIC1106PW PCM data size for the AIC1106 is 13-bit so New 3G module not support 13bits, and that is why we suggest to try 3254.

Does TLV320AIC1106PW support differebt for both S_DIN and S_DOUT?

This link was i posted before, FYI.
e2e.ti.com/.../737539

BRs

Eric Lo

0 Steve-Wilson over 7 years ago in reply to Eric Lo72350

TI__Mastermind 30240 points

BRs,

I don't believe the AIC1106 is any different. All of our Codecs behave this way with the exception of some of the devices that came from National Semiconductor like the LM49352 or LM49350.

The TLV320AIC3254 is a good device, but if they are not using the MiniDSP functionality, the TLV320AIC3204 or even the TLV320AIC3104 would be good choices too.

best regards,
-Steve Wilson

0 Eric Lo72350 over 7 years ago in reply to Steve-Wilson

TI__Intellectual 915 points

Hi Steve

So does TLV320AIC3254 support the function as below diagram?

The attached file is the pfw and cfg file that we setup, could you help to take a look if we miss anything?https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/6/2nd_5F00_case_5F00_Moderm_5F00_48KHz_5F00_16bit.7z

0 Eric Lo72350 over 7 years ago in reply to Eric Lo72350

TI__Intellectual 915 points

add diagram below

0 Eric Lo72350 over 7 years ago in reply to Eric Lo72350

TI__Intellectual 915 points

any comment from BU?

0 Steve-Wilson over 7 years ago in reply to Eric Lo72350

TI__Mastermind 30240 points

Eric,

Yes, I apologize for the delay. This cfg file is a mess. The comments do not match the commands.

from what I can tell, they are using both the HPOUTs and Left/Right LOP outputs. is that right? the PLL configuration seems fine, which is usually where people get caught up.
your diagram doesn't really show much. so its hard to know what they are trying to do or what they need.

best regards,
-STeve Wilson

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CCS/TLV320AIC3254: TLV320AIC3254 setting offset and bit clock question