Hi all
Would you mind if we ask TLV320AIC3100?
There is the description on the datasheet P65 as follows;
"When the ADC channel is powered down, ・・・When this flag indicates power down, the MADC divider may be powered down, followed by NADC divider."
<Question1>
When the ADC channel is powered down, are MADC and NADC powered down automatically?
<Question2>
If <Question1> is correct, when the DAC channel is powered down, are MDAC and NDAC powered down automatically?
<Question3>
In relation to <Question1> and <Question2>, when PLL configuration setting changes, ADC, DAC and PLL requires to be powered down.
Do NDAC, MDAC, NADC, MADC dividers require to be powered down individually?
<Question4>
If it requires to be powered down individually, is there any sequece between PLL's power down and NDAC/MDAC/NADC/MADC divider power down?
Kind regards,
Hirotaka Matsumoto