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TLV320AIC3100: P31 Table 7-17. ADC Processing Blocks

Hirotaka Matsumoto
Guru 27585 points
Part Number: TLV320AIC3100


Hi all

Would you mind if we ask TLV320AIC3100?

On the datasheet P31, there are some descriptions PROCESSING BLOCKS (PRB_R4～18), filter setting and AOSR.

<Question1>
In order to change Fs's value, we configure AOSR value.
At the same time, should we change the value "Page 0 / 「Register 61: ADC Instruction Set"?
The default value of "Register 61: ADC Instruction Set" is 0 0100: ADC signal-processing block PRB_R4, so it doesn't correspond for AOSR=32.

<Qusestion2>
In relation to ADC Processing Blocks of DAC, it seems that DOSR doesn't have any limitation.
Is it possible to set any value of "Page 0 / Register 60: DAC Instruction Set"?

<Qusestion3>
In relation to <Question2>, in case of changing "Register 61: ADC Instruction Set"'s value, is there any limitation and any sequences?
Or, during power down like as DAC and ADC on the datasheet P59 "Figure 7-34. Example Flow For Updating DAC Digital Filter Coefficients During Play", should we operate this action?

Kind regards,
Hirotaka Matsumoto

  • 0
    TI__Mastermind 30220 points

    Matsumoto-san, 

    please take a look at Table 7-17.  the Decimation filter for each processing block sets the limitation for the AOSR value. for AOSR of 32 only Processing blocks 16, 17 or 18 are available. there is a similar limitation on the DAC side with the interpolation filters.  

    Q2:  the DOSR only comes into play for the DAC processing blocks.  

    Q3: the ADCs must be powered down if changing the ADC instruction set value.  the same is true for the DACs.  you can follow the power down procedure for the DAC/ADC in the example flow if that helps you.

    best regards,

    -Steve Wilson