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PCM1865: SLAVE mode setting for only VINL1 and VINR1

Ando Ki
Prodigy 60 points
Part Number: PCM1865


I am using PCM1865 with 25Mhz Xtal input for reference clock and want to use PCM1865 as a slave by providing BCK and LRCK from external device.

I am looking for using PCM1865 at 44.1kHz sampling with 24-bit data.

Followings are status of related registers and it remains at "wait clock stable" of 0x72 and 'SCK_error" of 0x75.

       Adc1InputSelLeft(0x06): NORMAL VINL1[SE]
    Adc1InputSelRight(0x07): NORMAL VINR1[SE]
  PcmWordLengthRx(0x0B): 24-bit
  PcmWordLengthTx(0x0B): 24-bit
AudioSerialInterface(0x0B): I2S
               SckXtalSel(0x20): XTAL
MasterOrSlaveMode(0x20): SLAVE
  AutoClockDetection(0x20): DISABLE
       AdcClockSource(0x20): SCLK
    Dsp2ClockSource(0x20): SCLK
    Dsp1ClockSource(0x20): SCLK
                 PllControl(0x28): PLL enable; SCLK; Not locked
             PowerMode(0x70): Analog(Power Up) Device(Power Up) Digital(Run)
              FilterStatus(0x71): 2CH, DeciationFilter(Normal), HighPassFilter(Disable)
              MuteStatus(0x71): CH2_R(Unmute) CH2_L(Unmute) CH1_R(Unmute) CH1_L(Unmute)
           DeviceStatus(0x72): wait clock stable
SamplingFrequency(0x73): 32-48kHz
     BckClkDivStatus(0x74): 48
     SckClkDivStatus(0x74): 384
            ClockStatus(0x75): LRCK_halt(ok) BCK_halt(ok) SCK_halt(ok)
                                           LRCK_error(ok) BCK_error(ok) SCK_error(error)
          SupplyStatus(0x78): DVDD(good) AVDD(good) LDO(good)

Can anyone let me have a look of register settings for slave mode?

Or can anyone let me know how to do?

Thanks.

  • 0
    TI__Expert 5645 points

    Hello Ando,

    when you are running the PCM186x device in SLAVE mode, you do not need SCK input. As a result, you can remove the XTAL from your design. Also, can you please provide the BCK and LRCK clock freq values?

    You can run the device in AUTO config mode as well where by the internal clock source for ADC, DSP1 and DSP2 can be generated by PLL and you do not need to set any of the registers for clocks and PLL dividers. 

    Thanks.

    Best regards,
    Ravi

  • 0 in reply to Ravi Patil
    Prodigy 60 points

    Hi Ravi,

    Thank you for your reply.

    I use 44.1kHz sampling and BCK is 2.85MHz (Fbck) and LRCK is 44.6kHz (Flrck).

    These are derived from 100MHz system clock: 2.85MHz comes from 64*Fs and 44.6kHz comes from 64xFbck.

    I presume that Flrck should be the same as Fs.

    Even I set "CLKDET_EN" bit of REG32, "SCK_error" bit or REG117 remains 1, which means SCKERR.

    The DOUT always 0.

    What next I can do to fix this issue.

    Thanks.

    Ando.

  • 0 in reply to Ando Ki
    Prodigy 60 points

    By the way what is "AUTO config mode"?

    Does it mean setting "CLKDET_EN" of REG32 to 1?

    Thanks.

  • 0 in reply to Ando Ki
    TI__Expert 5645 points

    YES.

    If you use the BCK as your PLL source (by setting Register 0x28 - PLL_REF_SEL to '1'), and setting Register 0x20 - CLKDET_EN to '1', we can enable auto detect where the device is going to take the BCK as PLL source and set all dividers to generate ADC, DSP1 and DSP2 clocks. This is the easiest and simplest way to configure the device as the device is capable of calculating all the internal divider settings on its own.

    Best regards,
    Ravi

  • 0 in reply to Ravi Patil
    Prodigy 60 points

    Hi,

    According to the PCM196x datasheet, most of clock related bits are ignored when 'CLKDET_EN' is 1.

    This includes 'PLL_Enable' and 'PLL_REF_SEL' of REG_0x28.

    When 'CLKDET_EN' is 1, those bits could not change with writing through SPI port.

    Most of all, I did what you suggested already, but it still gave 0x00 for its output.

    Once again, here is the values of registers for PCM1865 Slave Mode.

           Adc1InputSelLeft(0x06:0x01): NORMAL VINL1[SE]
        Adc1InputSelRight(0x07:0x01): NORMAL VINR1[SE]
      PcmWordLengthRx(0x0B:0x44): 24-bit
      PcmWordLengthTx(0x0B:0x44): 24-bit
    AudioSerialInterface(0x0B:0x44): I2S
                    SckXtalSel(0x20:0x81): XTAL
    MasterOrSlaveMode(0x20:0x81): SLAVE
     AutoClockDetection(0x20:0x81): ENABLE
                     PllControl(0x28:0x00): PLL disable; SCLK; Not locked
                 PowerMode(0x70:0x00): Analog(Power Up) Device(Power Up) Digital(Run)
                  FilterStatus(0x71:0x1C): 4CH, DecimationFilter(Normal), HighPassFilter(Enabled)
                  MuteStatus(0x71:0x1C): CH2_R(Mute) CH2_L(Mute) CH1_R(Unmute) CH1_L(Unmute)
               DeviceStatus(0x72:0x01): wait clock stable
     SamplingFrequency(0x73:0x03): 32-48kHz
          BckClkDivStatus(0x74:0x37): 64
          SckClkDivStatus(0x74:0x37): 384
                 ClockStatus(0x75:0x01): LRCK_halt(ok) BCK_halt(ok) SCK_halt(ok)
                                                         LRCK_error(ok) BCK_error(ok) SCK_error(error)
               SupplyStatus(0x78:0x07): DVDD(good) AVDD(good) LDO(good)

    What error status of 'SCK_error' bit of Reg-0x75 means for? What  dose 'SCK_error' stand for while 'CLKDET_EN' is 1?

    As you can see PLL is disabled and not locked.

    Regards,

    Ando.