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Clocking the TLV320AIC3107 CODEC?

Terry61535
Prodigy 100 points


I am using the 3107 in conjunction with a Microchip dsPIC that uses a 10-MHz crystal as its clock.   The dsPIC is doing echo cancel and some other audio DSP functions and is connected via DCI to the 3107.  The 3107 datasheet says I can use BCLK in place of providing a separate MCLK.  As long as I set BCLK to say 1-MHz (higher than the 512-KHz minimum) is everything going to work fine?  Is this superior to trying to clock the Codec with an SPI clock  into the 3107 MCLK port (also at 1-MHz)?

  • 0
    TI__Mastermind 28585 points

    Any clock that meets the timing requirements for the PLL (or the divider) should work fine. If you don't have timing from a standard I2S source, you might want to use the AIC3107 as the master. This will insure that WCLK and BCLK are timed correctly for your programmed sample rate.

  • 0 in reply to Converter Apps
    Prodigy 100 points

    I am using the 3107 Codec to do 8-KHz sampling of speech (in and out) to keep things compatible with LEC and AEC DSP code that was designed for 8-KHz sampled data.  The optimal cost-complexity trade-off  for this design would be to clock the 3107 Codec with BCLK supplied by the dsPIC microcontroller, not a separate higher-speed MCLK. 

    What rate BCLK would you recommend  to be compatible with the PLL's in the 3107 and to stay above the 512-KHz minimum specified in the 3107 datasheet (page 25)?

    Are there any special issues related to setting up the 3107 PLL's when BCLK is used as its clock source? 

    Are there any additional programming guides or sample code available beyond those provided in the 3107 EVM that we purchased?

    Thanks, Terry

  • 0 in reply to Terry61535
    TI__Mastermind 28585 points

    Hi Terry,

     

    Any rate that meets the spec (512 kHz to 50 MHz) will work fine. In general, use the most stable clock you have available. The BCLK input can be used, it just needs to be selected in the registers. The software that comes with the EVM can be used to help pick the PLL settings.

     

    The main thing to remember is that the actual sample rate will be determined by the MCLK (BCLK in your case) and the PLL settings. The digital interface just clocks out the data and needs to be in sync with the data rate. For this reason, it is often easier to have the AIC3107 as the master so it will generate the interface timing.