TLV320AIC3110 beep generation

Rob,

Here is an application note regarding beep generation. 
http://focus.ti.com/lit/an/slaa446/slaa446.pdf

However, clock generation may be the problem.

Page 0
R4 = 0x03 (correct)
R5 = 0x91 (PLL powered up, P=1, R=1)
R6 = 0x07 (J= 7)
R7 = 0x14 (MSB of D = 0x14)
R8 = 0x90 (LSB of D = 0x90, D = 0x1490 = 5264)
R11 = 0x88 (NDAC Powered, NDAC Divider = 8)
R12 = 0x82 (MDAC Powered, MDAC Divider = 2)
R13 = 0x02 (DOSR = 0x0200)
R14 = 0x00 (DOSR = 0x0200)

Notice: R7 and R8 are not zero meaning the multiplier J.D will equal 7.5264.

With these settings your clocks are

PLL_CLKIN = 12 MHz
PLL_CLK = 90.3168
CODEC_CLKIN = 90.3168
DAC_CLK = 11289.6 kHz
DAC_MOD_CLK = 5644.8 kHz
DAC_FS = 11.025 kHz

Ensure the PLL multiplier and dividers are the values you want and double check that the clocks fall within the required ranges.  One helpful tool for calculating clocks is the AIC3254 or AIC3256 control software.  While it CANNOT control the AIC3110 you can use the Digital Settings > Clocks / Interface window to calculate the clock values easily.

Let me know if you have any questions.

Thanks,
Brian

Hello, I'm also having the same problem as the OP, where bit 7 of the p0/r71 is not cleared and no beep is heard.

I have a 12 MHz clock going to MCLK pin and no other signals driven (main CPU sound driver is not operational yet so no BCLK, WS, etc.)

The following is the sequence of commands I'm sending, originally copied from SLAA446.  I've set up the codec's GPIO1 pin to output a 48 kHz signal just to confirm that I'm communicating with the codec.  Anything obviously incorrect here?

e Initial conditions.
w 18 00 00 # Select page 0.
w 18 01 01 # Software reset.
s 1 # Wait a second.

e Set up PLL for 12 MHz MCLK source in, 98.304 MHz out (for 48 kHz sample rate)

w 18 04 03 # Set PLL_CLKIN=MLCK and CODEC_CLKIN=PLL_CLK
w 18 05 91 # Power up PLL with P=1, R=1
w 18 06 08 # PLL J=8 (J.D=8.1920)

w 18 07 07 # PLL D(msb)=0x07
w 18 08 80 # PLL D(lsb)=0x80
d 18 05 08 # Dump PLL settings.

e Set up clock dividers.
w 18 1B 01 # Mode=I2S, Word length=16, BCLK, WCLK are inputs to codec, DOUT Hi-Z.
w 18 0B 84 # NDAC powered up and set to 4
w 18 0C 84 # MDAC powered up and set to 4
w 18 0D 00 # DOSR=128, DOSR(9:8)=0
w 18 0E 80 # DOSR(7:0)=128
d 18 0B 0E # Dump divider register values.
w 18 12 84 # NADC powered up and set to 4
w 18 13 84 # MADC powered up and set to 4
w 18 14 80 # AOSR=128

e Set up clock repeater on GPIO1.
w 18 19 05 # CDIV_CLKIN is DAC_MOD_CLK (Fs x 128).
w 18 1A 80 # CLKOUT_MVAL=128 (CLKOUT = Fs).
w 18 33 10 # GPIO1 is CLKOUT.

e Set PRB & datapaths (what is this doing?)
w 18 3C 19 # DAC PRB set to PRB_P25.
w 18 3D 04 # ADC PRB set to PRB_R4.
w 18 3F D6 # Set the DAC datapath.

w 18 00 01 # Select page 1.
w 18 21 46 # De-pop, Driver power-on time=600ms, Step time=4ms
w 18 1F C6 # Power on HP drivers
r 18 1F # Check for short-circuit flag in b0.

w 18 23 88 # DAC_L routed to HPL, DAC_R routed to HPR
w 18 28 0F # HPL driver unmuted and gain set to 1dB
w 18 29 0F # HPR driver unmuted and gain set to 1dB
w 18 24 00 # Analog Volume control gain set to 0dB for HPL
w 18 25 00 # Analog Volume control gain set to 0dB for HPR
w 18 2E 0B # MICBIAS=AVDD
w 18 30 40 # MIC with Rin=10k
w 18 31 40 # CM with Rin=10k

e Mute settings
w 18 00 00 # Select page 0. This is missing in app note!
w 18 40 00 # DAC unmuted, independent volume control.
w 18 51 80 # Power ADC channel
w 18 52 00 # Unmute ADC channel

w 18 41 30 # LDAC gain 24 dB
w 18 42 30 # RDAC gain 24 dB
d 18 41 42 # Dump DAC gain settings

e Beep: 1kHz for 0.5 s at Fs = 48 kHz.
w 18 00 00 # go to page 0
w 18 49 00 # Beep length 0.5 s (500 cycles, 24000 samples).
w 18 4A 5D # ...
w 18 4B C0 # ...
w 18 4C 10 # Now writing Sine and cosine coefficients MSB first then LSB in register
w 18 4D D8 # ...
w 18 4E 7E # ...
w 18 4F E3 # ...
w 18 48 80 # Making gain of right beep same as left.
w 18 47 80 # Making gain of left channel 0dB and turning on the beep.
r 18 47 # Read beep control (reads 0x80)
s 1 # Wait 1 s.
r 18 47 # Read beep control. (reads 0x80)
s 1 # Wait 1 s.
r 18 47 # Read beep control. (reads 0x80)

w 18 1B 0D	# BCLK and WCLK is set as output from AIC3110
w 18 1E 88	# For 32 bit clocks per frame in Master mode ONLY