TLV320AIC3104: Low Power Analog Bypass Example with Output Driver Gain

Hi Jay,

There are a couple things to note here,

1. The passive analog bypass is not available to the HPOUT, these can only be routed to the LEFT_LOP/M or Right_LOP/M outputs.

2. in section 10.4.1 of the data sheet, three bypass path methods are described. only 10.4.1.2 and 10.4.1.3 are available on the AIC3104. The other is datasheet error (copy through from the AIC3106 which is the big brother to the AIC3104) the mode that is not available wouldn't have impact on your issue here as it would only have the ability to pass two single ended signals to the output blocks.

3. Since the passive analog bypass mode won't work here, the only other option is the ADC PGA bypass path. You will need to use a different input than line1LM. That is not a single ended input. I'd say just use MIC2R.

the inputs have a corse gain adjustment from -12 to 0. in 3 db steps. the PGA has more adjustment, but because you're mixing 3 signals you're going to have to get creative with how you balance the signals. if you just want them all summed, then that's no problem, if you want more individual control over each signal, that would be complicated.

# Route LINE2L to leftPGA, route LINE1L to left PGA, Route line2R to Right PGA.
w 30 11 0F
w 30 12 F0
w 30 13 00

# unmute left and right PGA
w 30 0F 00
w 30 10 00

# PGA_L to HPLOUT
w 30 2D 80

# PGA_R to HPLOUT
w 30 31 80

HPLOUT controls:
w 30 33 0D


best regards,
-Steve Wilson

Hi Steve

Thanks for that , I have managed to make some good progress, I have a few follow up questions:

1. How many single ended analog inputs can i have? I thought that all inputs could be used in a single ended confirgation (LINE2L, LINE1LP,
LINE1lM, LINE1RP, LINE1RM,LINE2R).

2. To adjust the output volume(HPLOUT), is it a matter of just adjusting the gain of register R51? Each of the 3 signals into the PGA will be line level
audio (~1VPP) and needs to be amplified to a level where it can be heard inside a headphone.

3. Is there any configuration required to get a single ended output (HPLOUT -> Speaker -> GND) or is this the default output format?

4. When using the analog PGA bypass, with up to 3 inputs what current reading should i be getting?

5. I have built an application circut based on figure 33 (Pg 84 of the datasheet). Is there a certain reason for the large number of caps on the power rails or they are just decoupling.

Thanks!

Jay

Hi Steve

Thanks for your reply!

1.) Thanks, thats the configuration i have just wanted to confirm

2.) Ok, that looks to be a much better method for volume control

3.) We are going to use headphones after some further discussion so this version of the chip seems perfect.

4.) I am attempting to measure the entire base current consumed by the system when used in th PGA bypass mode. I would like to confirm that my setup is correct in it reaching it minimum power draw and have a reference point.

5.) On the application circut based on figure 33, AVDD, DRVDD, DRVDD is all powered from the same 2.7 - 3.6V source however each pin has decoupling capacitors of the same value. Since all the pins are powered from the same 2.7 - 3.6V source, cant the power rail use a single 0.1uF, 1uF, 10uF capacitor in series rather than muliple capacitors of the same value in parallel?

Thanks for your prompt replies

Jay