Hi,
We are using the TLV320AIC3104 codec at the moment and are trying to use the PLL to generate the internal clocks from BCLK.
BCLK is 512KHz, fsref is 48000 and fs is 16000 so we can meet the
CODEC_CLK = 256 * fsref
criteria as described in section 10.3.3.1 of the 3104 datasheet.
We are using a K value of 48.0 [K = J.D where J = 48 and D = 0], R of 8 and a P of 2.
Now on page 24 it says:
‘When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz ≤ (PLLCLK_IN/P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R/P) ≤ 110 MHz
4 ≤ J ≤ 55 ’
Which seems to say that the BCLK of 512000 is invalid as 'PLLCLK_IN/P' is below the minimum 2MHz value. Even with a P of 1 we still don't satisfy the requirement.
Now the BCLK of 512000 is set by the bit rate :
data length in bits * 2 * sampling frequency = 16 * 2 * 16000 = 512000.
Am I right in thinking that BCLK needs to be left at 512000? or can it be multiplies of 512000 and still work?
If the BCLK must stay at 512000 then is the only solution to supply a MCLK to the codec to get this setup to work? If we do supply an MCLK does it have to be synchronized to the I2S BCLK so they use the same timing?
Regards,
