TAS5756M: LRCK and SCKI are synchronized ?("non-audio rate master clock "mode)

yoshimasa yazawa

Part Number: TAS5756M
Other Parts Discussed in Thread: PCM1808

Hi.
I'm planning sound system below.

I cannot provide audio rate clock to TAS5756M.

So I'll use TAS5756M "non-Audio rate master clock" mode like below diagram of datasheet.
("non-Audio rate clock" will be provided from microprocessor in my system....)

(TAS5756M Datasheet page 36)

I'm planning that using "New Audio MCLK" in above Figure.63 as SCKI of PCM1808 too.

According to PCM1808 datasheet, this device requires synchronization of LRCK between SCKI.

Like a below...

"7.3.3 Synchronization With Digital Audio System
In slave mode, the PCM1808 device operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6).
The PCM1808 device does not require a specific phase relationship between LRCK and SCKI, but does require
the synchronization of LRCK and SCKI."
(PCM1808 datasheet Page 15)

I worry about this.

The LRCK & MCK(new audio mck) from TAS5756M are synchronized?
(Do I need set some register to synchronize these?)

Thank you.

over 6 years ago

0 Xiaolin Qin over 6 years ago

TI__Expert 6295 points

for TAS5756, you can use internal PLL as MCLK input. just three I2S wire input could be ok. does this address your worry?

0 yoshimasa yazawa over 6 years ago in reply to Xiaolin Qin

Prodigy 100 points

Hi, Qin.
Thank you for your reply.

I know that TAS5756M can be used internal PLL as MCLK.
As shown as below diagram,right?

I recognize this mode is used when the TAS5756M works as Slave mode.
Because PLL needs receive SCLK,GPIO or MCLK as base clock in this case.

I wanna use TAS5756M as master mode.
Because PCM1808 is exist in my design, this device needs audio rate clock as master clock (SCKI pin),but the microprocessor in my design cannot provide audio-rate clock.

And, according to datasheet of PCM1808, it requires master clock(SCKI pin) input synchronized with LRCK.

According to TAS5756M's datasheet, it can provide audio-rate master clock via PLL from non-audio rate master clock as shown below("New Audio MCLK").

So, I guessed as "New Audio MCLK" can be used as master clock (SCKI pin) of PCM1808 too.