TAS5766M: reset timing

Mike Rudeen

Part Number: TAS5766M

Hi TI,

Figure 32 in rev D of the TAS5766 data sheet shows an internal power-on reset signal that must expire > 4ms after the I2S clocks are applied. I have several questions about this:

How long does the internal reset pulse stay active after 3.3V is in tolerance?
Does the part need all three I2S clocks (SCLK, BCLK, and LRCLK) or just SCLK to be operating when the internal reset is asserted?
If I execute a software powerdown (via page 0, Register 2, bit 0 set to 1), does this do the same function as the power-on reset?

Thanks in advance for your help,

Mike

over 6 years ago

0 Xiaolin Qin over 6 years ago

TI__Expert 6295 points

shutdown sequence see figure47 and 48. for other two questions, let's get some internal check, then reply to you

0 Mike Rudeen over 6 years ago in reply to Xiaolin Qin

Prodigy 30 points

Hi Qin,
Thanks for your reply. I will look forward to your answers on the reset timing from figure 32.

MIke

0 Mike Rudeen over 6 years ago

Prodigy 30 points

Hi TI,
Any more information? WE had another thought this morning that perhaps the internal reset width is not timed at all but rather counts clocks for 4ms per the figure 32 in the data sheet and then removes the internal reset? Can you please confirm or deny this thought?

Thanks,
Mike

0 Alix Wan over 6 years ago in reply to Mike Rudeen

TI__Genius 9995 points

Hi Mike,

When DVDD is higher than 2.8V, internal power-on reset will be triggered itself. Then digital core will be active. At this time, DVDD reached 3.3V and I2S starts to work. Once upon digital core detects the valid I2S (I2S clocks are a reference to internal pll), it begins to count and then 4ms later. The internal reset is disabled.

Regards,
Alix Wan.

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TAS5766M: reset timing