Can someone help me resolve an issue with the TAS5766M SmartAmp we can’t seem to get around in our new custom design?
In this new design, we’ve connected the SmartAmp’s SCK input to a Precision Clock Generator (PCG) block output on our DSP, so the SmartAmp doesn’t have a SCK upon power-up until this DSP configures its PCG to provide a 12.288 MHz clock (along with 1024 kHz BCK and 16 kHz LRCK clocks) from a 24.576 MHz external oscillator. We’ve found that the SmartAmp must be sent into power-down mode by setting the I2C page 0 register 2 bit 0, clearing it, and delaying 10 ms to see any I2S data come out from the SmartAmp’s SDOUT (via GPIO3) signal. However, even with this SDOUT data coming from the input to the DAC, we don’t see any modulation of the power amp’s OUTPR/L signals because the INPR (cap-connected DACR) signal is at a constant DC level (biased at 3.3V). The problem seems to be the DAC isn't converting the audio samples at its input (as SDOUT shows) to an analog input signal to the Smart Amp's built-in power amp to modulate an (observed) 768 kHz PWM signal at (which just looks like high voltage 50% duty cycle clock).
Any suggestions appreciated.


