SRC4392: None of RX ports working, only Port A and B and TX output

Dear Andy,

You are right, I had on my mind that I needed to use two different clocks for different input sample rates on DIR, but actually not. Using 24.576Mhz works for 44.1 and 48kHz sample rates. Actually only need to change it for DIT output sample rate. I think I missunderstood something on the datasheet.

Lock pin, RDY, and INT are connected to Microcontroller so I can easily read them in any case. But actually found the problem, the buffer used for TTL input was forcing low the optical input, really weird... after desoldering buffer, works like a charm..  It's really strange this happens, to me my schematic looks good.

Thank you so much for your support!

Oriol.

"I need to use both TTL and optical inputs at "same" time, that tmeans that user no needs to use jumpers or something similar. Any help on this?"

Basically, you can't. Only on RX input can be decoded at a time.

There is a mux that selects which RX input drives the AES3 decoder. The DIR can decode only one input at a time. The output of the DIR can feed the SRC, the DIT or either of the Audio Serial Ports (I2S). For this to work, though, your design has to select the desired input. It cannot autodetect which input to use. Consider two valid AES streams on two of the RX inputs -- how can the chip decide? So at the least you need to provide a user interface which lets your user choose which RX input to use, and based on that choice you program register 0x0D Receiver Control Register 1.

Now, there is the Bypass Mux, which lets you select any of the four RX inputs to drive the AES and TX± outputs directly without going through the AES decoder and encoder. But this of course means you can't use the TX output for anything other than that direct input.

Dear Andy,

Thank you so much for your response. Unfortunately I think you have not understood correctly my question, or probably I was not so clear explaining the situation!

The design has 4 optical inputs, that also allows to use coax if user wants to use it instead of optical input. So coax and optical shares same RX input, of course! User obviously cannot connect Optical and Coax at same time, I just want to give the user the possibility to use the one he/she wants.

So, in addition, there are four TTL inputs, that user can also use in case don't want to use Optical or Coaxial. Or just because the user requeriment matches using TTL inputs.

Now the problem here relays that TTL buffer is forcing low the RX inputs, so that's why I was not able to get Optical and Coax inputs working. When desoldered buffers from the board, inputs start to work. 

So just asking why I'm having this behaviour on the buffer, because there's should be no problem at all with that (you can check my design above with input buffers). Input is floating, bout output shoudn't be forced to zero, isn't it? I'm stuck here!

Thank you!

Andy Peters said:

"I know that is High Z output if output is not enabled, but if it's enabled and input is floating? Shouldn't be output too?"

From the SN74LVC1G125 data sheet, page 12, section 12.1 Layout Guidelines: "All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating."

In other words, never let a CMOS input float. This advice goes back to the beginning of time. A weak pull-down or pull-up resistor, something easily overcome by a connected driver, should be put on the input if there is ever a chance that the input will be undriven.

Thank you Andy,

I will solve this issue using more buffers in combination of 125 and 126, so when one is enabled the other one is disabled, this way will cause no troubles between TTL and Optical/Coax inputs.

What about my other question?

Oriol said:

Also regarding this, it should work the same way as DIR? I mean, using only one clock frequency I'm able to re-sample all input sample rates, 44.1 and 48kHz ones, without the need to change to specific sample rate clock. Port A and B should work the same way? Because as far as I see I need to switch from one clock to another to play files using I2S signals on Port A and B, doesn't work the same way as DIR. But this change also makes me change all the init setup everytime user uses a diferent sample rate. So I do not have a clear idea of how actually the SRC works here.

Also if I want to re-sample to 88.2kHz for example, instead 96kHz, I can still use the 24,576 clock? As far as I know I need to switch to the 22.5792 one. That's why I do not understand correctly this part, because DIR can accept any sampling rate using only one clock, but DIT not?

Thank you so much!

Oriol.

Can anybody help me please?

Running SRC4392 in I2S slave mode only plays 48kHz sample rates files, even using the 22.5792 clock as reference. Why? I'm stuck on this!

Thank you,

Oriol.