TAS2505-Q1: I2C minimum SDA/SCL rise/fall time

Masatoshi Oguri

Part Number: TAS2505-Q1

Hello,

The I2C timing requirements have rise/fall time for SDA/SCL. This is unusual for I2C specs, and my customer is not meeting it right now. Is there any unwanted behavior expected when violate it? Say particularly with 500ps rise/fall time, what wrong is expected? This information is necessary for the customer to consider a fix.

Thank you.

Regards,

Oguri (TIJ automotive FAE)

over 6 years ago

0 Ivan Salazar over 6 years ago

TI__Guru** 109825 points

Hi Oguri-san,

Has customer tried their I2C interface already and its facing issues?
The time spec is the standard I2C (_ e2e.ti.com/.../TCA9535_2D00_2.JPG _), TAS2505-Q1 has a standard I2C interface.
Do you know if customer is using standard-mode or fast-mode?

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

0 Masatoshi Oguri over 6 years ago in reply to Ivan Salazar

TI__Expert 4780 points

Hi Ivan,

Thanks!
I did not know that.
There is no actual problem, but the customer is concerned of spec violation.
That is fast-mode.

Regards,
Oguri

0 Ivan Salazar over 6 years ago in reply to Masatoshi Oguri

TI__Guru** 109825 points

Oguri-san,

I think this should keep working fine, as long as both sides of I2C communication are standard I2C interfaces.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

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TAS2505-Q1: I2C minimum SDA/SCL rise/fall time