• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 31 subscribers
  • Views 1181 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TAS2505-Q1EVM: The parameters questions for DAC class-D amp playback configuration

Nick Hsiao19
Intellectual 645 points

Part Number: TAS2505-Q1EVM
Other Parts Discussed in Thread: TAS2505-Q1, TIDA-01529, TAS2505EVM

Hi Team,

My application of TAS2505-Q1 is to be an I2S slave without MCLK. According to the suggestion of the manual, the clock parameters are:

  1. BCLK = 1.536MHz (=PLL_CLKIN)
  2. R*J.D/P = 4*14.0/1 (R=4, J=14, D=0, P=1)
  3. CODEC_CLKIN = PLL_CLK = 86.016MHz
  4. NDAC = 2, and the DAC_CLK = 43.008MHz (much higher than EVM 6.144MHz)
  5. MDAC = 7, and the DAC_MOD_CLK = 6.144MHz
  6. DOSR = 128, and the DAC_fs = 48kHz

My power supply configuration is using 5V SPKVDD to generate internal LDO 1V8 for both DVDD and AVDD, and external 3V3 to IOVDD.

 

I have checked the parameters met to each equations list in manual, but I still have some questions:

  1. What is PLL “R” range? 1~4 or 1~16? It is irregular in the datasheet.
  2. What is “DAC_CLK” purpose? Is it just a clock source of BDIV_CLKIN?
  3. What is “BDIV_CLKIN”? If I do not have clock output, is it necessary to me?
  4. What will happen when I2S interface is off without reset the register? I mean, the I2S (BCLK\WCLK\DATA) from processor is not always fed into TAS2502-Q1, should I do power down sequence every time the I2S is off? Or just keep the configuration til next I2S coming?
  5. The EVM default class D playback example is a little bit different and weird to me, although it works for EVM. Could you please check it for me? As the attachments. (some parameters in registers are reserved, but the example config tries to write value on it. i.e. page 0, reg 0x3F, D3-D2. Example write value 0xB0, but I think 0xB4 is correct)
  6. What is “Master Reference” in the reg 1, page 1?
  7. The schematic of EVM is connecting LDO_SEL to SPKVDD, but the example write LDO select D0 (reg 2, page 1) to 0 (LDO_SEL pin is low). Though EVM still works, but the value should be 1 (LDO_SEL is high), am I right?

ClassD_playback_example.cfgPGWW20_ClassD_playback.cfg

  • 0
    TI__Guru* 84915 points
    Hi, Nick,

    Please take a look at my answers below and let me know if you still have questions or comments on this.

    1.- You are right. The "R" value seems to be specified as 1-4 by registers settings and 1-16 in the PLL section of the Reference Guide. The correct range is 1-4. We will work to modify the incorrect range as soon as possible. Just a reminder, when D ≠ 0, R must be R = 1 due to some restrictions in the PLL.

    2. The DAC_CLK can be the clock source of the BDIV_CLKIN, but it also works to initialize the processing blocks. All the audio converters with integrated processing blocks require of a clock to be initialized. Some cases with integrated beep generator require of the DAC_CLK working all the time. In some other devices such the TAS2505-Q1, they only require of few DAC_CLK pulses to be initialized.

    3. BDIV_CLKIN is only required when the BCLK is configured as output. This clock source takes the DAC_CLK or DAC_MOD_CLK as source to generate the BCLK. It is not required in slave mode.

    4. There's no need to disable or reset the registers when the I2S lines are disabled. The device is muted when no data is available. The same registers settings can be kept until next I2S data is available. However, the device consumes power when the DAC and output drivers are powered up. We usually recommend to power off these blocks to save power in standby mode.

    5. I agree. Register 0x3F must be 0xB4 since the bit D2 is reserved and must be always '1'. This is a typo error on the EVM default settings that doesn't seem to affect the normal behavior significantly.

    6. The master reference works as the Headphone driver power reference. This is necessary when the Headphone driver is intended to be used. The Class-D output doesn't require this reference to work.

    7. Are you using the TIDA-01529 (Cluster and eCall Audio Reference Design With Diagnostics)? It seems that the registers configuration that you are using is designed for the TAS2505EVM RevA ( www.ti.com/.../slau498a.pdf ), which allows to connect LDO_SEL pin to either SPKVDD or GND. This registers configuration works correct for both evaluation modules, but in case of the Page 1, Register 2, Bit D0 must be 1 for the TIDA-01529 (LDO_SEL is set high as you mentioned).

    I hope this helps you. Please let me know if you still have questions or comments on this device. We will work to correct the typo errors that you detected in order to avoid future confusions.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 645 points
    Hi Luis,
    It is really helpful to me. I have further replies, please check it below:
    2. In my design, DAC_CLK = 43.008MHz which is much higher than EVM design (6.144MHz), Do you have the recommend DAC_CLK range?
    7. Yes, I am using TIDA-01529 instead of TAS2505EVM.

    Thanks for the prompt reply~
    Nick.
  • 0 in reply to Nick Hsiao19
    TI__Guru* 84915 points
    Hi, Nick,

    2. The DAC_CLK frequency range depends of the DVDD voltage level. The DAC_CLK frequency can be supported up to 25MHz if DVDD ≥ 1.26V or 55.296MHz if DVDD ≥ 1.65V. For more details, please take a look at Table 2-21 of reference guide: www.ti.com/.../slau434a.pdf

    7. The TAS2505EVM has more flexibility in hardware configuration due to different jumpers configuration. The registers configuration that you are using works correctly for this EVM and the TIDA-01529. I just recommend to modify the page 1 / register 2 as you mentioned in your first post.

    Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 645 points
    Hi Luis,
    Sorry for the late reply.
    Thanks for the advice, it would really help me a lot.

    Regards,
    Nick.