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TLV320AIC3262: Glitches related to AGC

Part Number: TLV320AIC3262

We have a rather old design that we're trying to enable AGC on.  We are recording a left channel on IN3L and a Right channel on IN3R.  Both are at mic level.

We noticed that most of the time the AGC works and gives us audio on both channels.  However, sometimes one channel will stop recording audio (basically muted) while the other continues recording.  I have noticed that when this happens, the read-only AGC gain register for that channel (0x5D for left, 0x65 for right) will get stuck at a value of 0xE8, which is the minimum possible gain value of -12dB.  This register will stay stuck at -12dB until we power cycle the unit and re-initialize the codec, and the gain will never automatically increase to try to hit the target level.  Until we re-initialize, the audio on that channel will be gone.  Generally no other registers on Page 0 or Page 1 are affected when this glitch happens.

It seems like a bug in the codec, because we are not sending the codec any commands that should be making it reduce the gain.  What could cause the codec to think it needs to apply -12dB gain?

  • Arthur,

    If the signal input has a large swing above the Target Level, the AGC will attack and lower the PGA gain. The AGC has several parameters that control when the PGA gets changed. Depending on the setting of these parameter and the input signal level, these might cause the AGC to avoid changing PGA values to prevent audible artifacts. Check your settings for Noise Threshold, Hysteresis, Noise and Signal Debounce times. If the signal is close to the Noise Threshold (within the Hysteresis value), the AGC might think the signal is noise and avoid changing PGA values. If the signal crosses the Noise Threshold but falls back below it within the Signal Debounce Time, the AGC will not change the PGA.

    A few more suggestion to help debug the issue:
    - Connect both channels together to the same input signal during your test to see if the problematic behavior occurs in only one channel.
    - Repeat the test, flipping the input channels, to see if the second channel exhibits the same problematic behavior as the first channel.
    - Check power supplies for glitches when the problem occurs.
    - Check clocks for glitches when the problem occurs.

    This application note has detailed descriptions of the AGC parameters and its function and might be helpful in debugging your problem:
    www.ti.com/.../slaa446.pdf

    best regards,
    Pedro
  • Pedro,

    How do these parameters look? Noise threshold is disabled.


    /* AGC PARAMETERS */
    00 00 56 D2 /* Left AGC: Enabled = True, Target Level = -17.0 dBFS, Gain Hysteresis = +/- 1.0 dB */
    00 00 5E D2 /* Right AGC: Enabled = True, Target Level = -17.0 dBFS, Gain Hysteresis = +/- 1.0 dB */
    00 00 57 00 /* Left AGC: Hysteresis = 1.0 dB, Noise Threshold = Disabled */
    00 00 5F 00 /* Right AGC: Hysteresis = 1.0 dB, Noise Threshold = Disabled */
    00 00 58 50 /* Left AGC: Max Gain = 40.0 dB */
    00 00 60 34 /* Right AGC: Max Gain = 26.0 dB */
    00 00 59 38 /* Left AGC: Attack Time = 10.00 msec */
    00 00 61 38 /* Right AGC: Attack Time = 10.00 msec */
    00 00 5A 38 /* Left AGC: Decay Time = 160.00 msec */
    00 00 62 38 /* Right AGC: Decay Time = 160.00 msec */
    00 00 5B 01 /* Left AGC: Noise Debounce Time = 0.0 msec */
    00 00 63 01 /* Right AGC: Noise Debounce Time = 0.0 msec */
    00 00 5C 01 /* Left AGC: Signal Debounce Time = 0.0 msec */
    00 00 64 01 /* Right AGC: Signal Debounce Time = 0.0 msec */


    I want to emphasize that the AGC gets put somehow into a bad state. It doesn't momentarily act up, it gets permanently stuck at low gain until we reset everything. Sometimes the recorded channel that gets stuck will record with a DC offset and will remain that way indefinitely. After a software reset everything is restored to normal.
  • Arthur,

    The parameters seem fine. I see left channel has greater gain than right channel. Have you swapped the channels to see if the same issue happens on the other channel? Have you tried other combinations of Attack and Decay time? Have you tried enabling the Noise Threshold? Disable Hysteresis?

    I understand your concern about a problem with the AGC algorithm. I am trying to determine if it is specific to a channel, setting, input amplitude. The other possibility is that there is something in particular with the input signal that forces the algorithm to set the gain to -12db due to the settings of hysteresis, decay time, noise threshold, max gain, etc.

    Best regards,
    Pedro
  • Pedro,

    Both channels exhibit the issue sometimes with these settings so no need to swap channels.  The left channel gain is different from the right channel gain because the application isn't "stereo" audio, there's some analog filtering happening on the right channel, but not on the left, that the original designers were trying to compensate for.  I'll PM you and send a schematic.

    To aid my debugging efforts, could you explain what the AGC algorithm would do if there was a DC offset on the incoming audio signal to the codec?

    Thanks,

    Arthur

  • Arthur,

    The AGC algorithm has a high pass filter to remove DC component. After the high pass filter, the AGC estimates the average absolute value of the input signal to determine the average energy and computes the gain based on this energy level. Application of the gain is dependent on the attack and decay time. This gain change is only applied if the signal is above the noise threshold and past the hysteresis of the threshold values.

    Does the gain get stuck in the channel that does not have the analog filtering? If so, what is the analog filter? My first thought is that some very low frequency component is trowing off this energy estimate and is not attenuated enough by the AGC's high pass filter.

    best regards,
    Pedro
  • Pedro,

    Both channels can get stuck, it's not purely one or the other. Could you accept my friend request so I can PM you schematics and details?

    Thanks,
    Arthur
  • Arthur,

    The Signal Processing Blocks of the ADC3262 include a 1st Order IIR Filter just prior to the AGC. The default setting of the 1st Order IIR Filter is an all pass with flat gain of 0dB. Thus, by default it is not performing a DC block. You could change the coefficients of this filter to block the low frequency components to prevent any DC biasing of the AGC energy estimate. Section 2.4.3.2.1 of the TLV320AIC3262 Applications Reference Guide show the transfer function and the programmable coefficients. 

    best regards,

      Pedro