PCM3168A experts,
One of our customers is looking to configure the PCM3168A to act as a slave on the I2S/TDM port, with the Audio Clock master providing:
SCKI = 24.576 MHz
Bit Clock = 12.288 MHz
LRCK = 48 kHz
6 channels "in" (ADC to DOUT1) and 8 channels "out" (DIN1 to DAC)
Bit clock is running at 32 bits/sample, while only 24 bits are used per sample, and the 24 bits are left justified.
I believe this lines up with Figure 1, Single Rate, 48 kHz, 512 fs, 24.576 MHz. And Figure 52, Left Justified Single.
Can you confirm for me that this is a valid configuration for this device?
What should the settings be for:
FMTDA[3:0] in register 65
FMTAD[2:0] in register 81
Thanks,
Darren
