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TAS5720M: Where is the problem if the SAIF clock error(register 0x08, bit 3) and FAULTZ pin pulses low for 10 μs every 350 μs

Part Number: TAS5720M

Hello, 

We are using and debugging TAS5720 for our new product as the CODEC. But it get SAIF clock error, and I measured the FAULTZ pin, it pulses low for 10us every 350us. 

The register read is as follow,

00   01
01   fd
02   04
03   80
04   ff
06   55
08   08
10   ff
11   fc

In the tas5720M manual, there is a description like this, 

While operating in shutdown mode, the SAIF clock error detect circuitry powers down and the CLKE bit reads
high. This reading is not an indication of a SAIF clock error. If the device has not entered active mode after a
power-up sequence or after transitioning out of shutdown mode, the FAULTZ pin pulses low for only
approximately 10 μs every 350 μs.

So what is the cause of the problem? It means the tas5720m never enter active mode or fail to transit to active mode. Generally, what makes tas5720m not enter active mode, is the MCLK error or the hardware error?

The working conditions:

- SAIF: I²S

- 64-Bit Frame, 16-Bit Data,

- FS= 44,1 kHz

- BCLK = 3170 MHz

- MCLK= 2910

But I don't think the problem has anything to do with the working conditions. Because before the I2S transfer, the SAIF clock error and FAULTZ pin pulse low for 10us has existed.

Best Regards,

Zhangjs

  • hello,

    there is some question point about I2S input for TAS5720:

    are you sure BLCK is 3170MHZ? not 3.17MHZ? how about MCLK unit? you may need to make sure SAIF meet datasheet requirements.

    The valid MCLK to LRCLK ratios are 64, 128, 256 and 512 as long as the frequency of MCLK is 25MHz or less.

    regards
    Linda
  • Hello,

    Sorry for the mistake. The bclk is 3.17MHz, which is the measured value.

    Yes, the milk to lrclk ratio should be 64, 128, 256 or 512. In my project, the input audio fs is 44.1Mhz, so the input lrclk frequency is also 44.1k. We set the milk frequency to 44.1*64 = 2822khz. But due to the deviation of the cpu frequency division, the generated PWM for mclk is not exactly equal to the expected. The actual measured mclk frequency is 2910 kHz, which is a little deviation from the expected.

    Also, the bclk is also a little deviation from the set value. We are using the nxp imx 6 cpu as the controller, the mclk is generated by the pwm , while the Bclk is generated by the Sai/I2S peripheral.

    Do you have any suggesstion about the deviation of the cpu frequency division?

    Best regards,
  • Hello,

    The manual says “This reading is not an indication of a SAI clock error.”. So what do you think about the error?

    Best regards,
  • Hi Customer,

    BLCK=64*LRCLK=64*44.1K=2.822MHz. Hence, you should configure BCLK of SoC to meet the ratio. Please see page 6 of the datasheet.
    Now that clock error exists during power on, the issue cannot go out by entering active mode.

    Regards,
    Alix Wan.