Hi Team,
My customer would like to confirm about description of SDA hold time in clause "7.6 Timing Requirements for I2C Interface Signals".
In the table, minimum value of Data hold time th(1) is defined as 0ns with notation below.
"(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL."
Does above notation mean as bellow?
a) As timing requirement for I2C master, TAS5411-Q1 doesn't require hold time.
b) TAS5411-Q1 generates hold time internally to avoid uncertain falling edge of SCL.
Best regards,
Nobuo Fujihara
