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TLV320ADC3101: Question of TLV320ADC3101 PRB2 Coding

Part Number: TLV320ADC3101


Hi Sirs,

Customer encounters an ADC3101 PRB2 coding problem which needs product line's suggestion. The CFG source is:
When we wrote "w 30 51 c0" (line 35), the page 4 data will be cleared to zeros. Would you please assist us to review if there is missing or mistake with the CFG?   

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01 - # Device Initialization
02 -  w 30 00 00 # Page 0
03 -  w 30 01 01 # Reset
04 -  w 30 3D 01 # Processing Block PRB_R1

05 - # Clock configuration.
06 -  # MCLK = CLKIN = 2.048MHz
07 -  # WCLK = Fs = 8KHz
08 -  # BCLK = 64×Fs = 512KHz
09 -  w 30 12 81 82 # NADC 1, MADC 2
10 -  w 30 1D 03 # BDIV_CLKIN = ADC_MOD_CLK (1.024MHz) / N
11 -  w 30 1E 82 # BCLK = 1.024MHz/2 = 512KHz
12 -  w 30 1B 4C # BCLK and WCLK are outputs in DSP mode (Master mode)

13 -  # Micbias Configuration
14 -  w 30 00 01 # Page 1
15 -  w 30 33 50 # MICBIAS 1/2 = 2.5V

16 -  # Digital Mic Configuration
17 -  w 30 00 00 # Page 0
18 -  w 30 33 28 # DMCLK = ADC_MOD_CLK (required for DMIC operation)
19 -  w 30 34 04 # DMDIN is the input for DMICs
20 -  w 30 50 02 # DMIC L-Ch read at DMCLK falling edge, R-Ch at rising edge
21 -  w 30 51 CE # ADCs ON, DMIC is enabled on both channels, Soft-stepping disabled
22 -  w 30 52 00 #ADCs Unmuted

23 -  w 30 00 00
24 -  w 30 53 28
25 -  w 30 54 28

26 -  w 30 00 00
27 -  w 30 3D 02
28 -  w 30 51 00
29 -  w 30 00 04
30 -  w 30 0E 7F AA 80 56 7F AA 7F AA 80 AB 7F FF 7F FF 7F FF AE 51 C3 16 7F FF 00 00 00 00 00 00 00 00
31 -  w 30 2C 7F FF 00 00 00 00 00 00 00 00 7F FF 00 00 00 00 00 00 00 00
32 -  w 30 4E 7F AA 80 56 7F AA 7F AA 80 AB 7F FF 7F FF 7F FF AE 51 C3 16 7F FF 00 00 00 00 00 00 00 00
33 -  w 30 6C 7F FF 00 00 00 00 00 00 00 00 7F FF 00 00 00 00 00 00 00 00
34 -  w 30 00 00
35 -  w 30 51 C0
36 -  w 30 52 00

37 -  # Digital Mic Configuration
38 -  w 30 00 00 # Page 0
39 -  w 30 33 28 # DMCLK = ADC_MOD_CLK (required for DMIC operation)
40 -  w 30 34 04 # DMDIN is the input for DMICs
41 -  w 30 50 02 # DMIC L-Ch read at DMCLK falling edge, R-Ch at rising edge
42 -  w 30 51 CE # ADCs ON, DMIC is enabled on both channels, Soft-stepping disabled
43 -  w 30 52 00 #ADCs Unmuted

44 -  w 30 00 00
45 -  w 30 53 28
46 -  w 30 54 28

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Thank you and Best regards,

Wayne Chen
05/28/2019