TAS2559: Datasheet: Incomplete register specification

Frank Rolsted Jensen

Part Number: TAS2559

Ref. Datasheet: "TAS25595.7-W Class-D mono audio amplifier with class-H boost and speaker sense with stereo processing", NOVEMBER2016–REVISEDFEBRUARY2019.

The Datasheet seems to be incomplete or outdated.

Some register specifications contain reserved bit fields. However, some of these bit fields are used in the android driver and by PPC.

Reserved bit fields in register b0p0r22 (DSP_CTRL) are used in the datasheet (chapter 9.6.2) without any description.

Reserved bit fields in register b0p0r2f (ASI_CTRL_2) are set by PPC.

Reserved bit fields in register b0p0r07 (MUTE) are set in the android driver without any description.

Further more, the android driver is using unspecified registers, e.g. b64p0r40 (TAS2559_VBOOST_CTL_REG) and b0p2r7 (TAS2559_SLEEPMODE_CTL_REG).

The description of the PLL registers are also missing and a clock tree diagram would be very useful when configuring the PLL, clock source, clock dividers etc.

over 5 years ago

0 Luis Fernando Rodriguez S. over 5 years ago

TI__Guru* 84915 points

Hi, Frank,

Welcome to E2E and thank you for your interest in our products!

I will take a look at this and will answer as soon as possible.

Best regards,
Luis Fernando Rodríguez S.

0 Luis Fernando Rodriguez S. over 5 years ago in reply to Luis Fernando Rodriguez S.

TI__Guru* 84915 points

Hi, Frank,

Could you provide additional details about the bits that are configured even if they are marked as "reserved"? Some of the bits of the registers that you mentioned are not reserved and must be configured when they are used by the Android driver or PPC.

Best regards,
Luis Fernando Rodríguez S.

0 Frank Rolsted Jensen over 5 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 140 points

Hi Luis,
Yes, here are some examples:

1. The Datasheet, chapter 9.5.2 includes following line:
w 98 22 22 # use default coefficients and operate DSP in rom mode 2

According to the datasheet only bit 0:3 are defined. Bit 5 is reserved.

2 PPC sets register b0p0r2f to 0x2a in the PRE section (mode 1 configuration)
# PRE begins
w 98 00 00
w 98 7f 00
w 98 2f 2a
(...)

According to the datasheet only bit 0:1 are defined in this register.

3. The Android driver [1] is using some undefined registers in function: tas2559_set_VBoost()
- TAS2559_VBOOST_CTL_REG
- TAS2559_SLEEPMODE_CTL_REG
- TAS2559_VBST_VOLT_REG

4. The Android driver [1] is using a undefined register in function: tas2559_SA_DevChnSetup()
- TAS2559_SA_CHL_CTRL_REG

5. PLL registers are unspecified
All PLL registers in the PLL block (output from PPC) are unspecified.
TAS2559 Technical documents [2] refers to a document describing the PLL and clock configuration ("PLL and Clocking Configuration for Audio Device" [3]), but this document does not include a description of the TAS2559 codec (?).

/Frank

[1]: git.ti.com/.../tas2559-core.c
[2] www.ti.com/.../technicaldocuments
[3] www.ti.com/.../slaa892.pdf

0 Luis Fernando Rodriguez S. over 5 years ago in reply to Frank Rolsted Jensen

TI__Guru* 84915 points

Hi, Frank,

Some of the reserved registers that you mentioned are related to internal specific DSP activity. After some research, I found the information below:

1.- w 98 22 22 # use default coefficients and operate DSP in rom mode 2

Bit 5 can be written in order to determine if the ZROM is copied to YRAM on DSP power up.

0 : Default coefficients from ZROM are not copied to YRAM on dsp power up
1 : Default coefficients from ZROM are copied to YRAM on dsp power up

2.- 2 PPC sets register b0p0r2f to 0x2a in the PRE section (mode 1 configuration)

Bits D7-D3 are related to the current sense delay.

0: delay isense ADC output by 0 adc mod clk cycles
1: delay isense ADC output by 1 adc mod clk cycles
2: delay isense ADC output by 2 adc mod clk cycles
...
...
...
15: delay isense ADC output by 15 adc mod clk cycles
16: delay isense ADC output by 16 adc mod clk cycles

3.- B0_P2_R05.

- TAS2559_VBOOST_CTL_REG

This is not fully described, but it seems to be related to the ramp VBOOST ramp.

Bits D7-D5:

0: Ramp Height = 6.7. Boost div = 14, (ramp_bst_div_reg)
1: Ramp Height = 5.8. Boost div = 12, (ramp_bst_div_reg)
2: Ramp Height = 5.3 (Vboost < 6.5V). Boost div = 11, (ramp_bst_div_reg)
3: Ramp Height = 4 (Vboost < 5). Boost div = 8.3, (ramp_bst_div_reg)
4: Ramp Height = 7.7. Boost div = 16, (ramp_bst_div_reg)
5: Ramp Height = 8.5. Boost div = 17.7, (ramp_bst_div_reg)
6: Ramp Height = 8.9. Boost div = 18.7, (ramp_bst_div_reg)
7: Ramp Height = 10. Boost div = 21, (ramp_bst_div_reg)

Bits D4-D0. Reserved.

- TAS2559_SLEEPMODE_CTL_REG

This one is related to the power saving modes.

D7: en_sleep_mode_dac
D6: en_sleep_mode_boost
D5: en_sleep_mode_vsns
D4: en_sleep_mode_isns
D3: 0: en_dac_pwr_save_reg = 0
1: Force enables the power save mode of DAC. en_dac_pwr_save_reg = 0
D2-D1 0 All Values Reserved. Do not write non-default values
D0 0 … sleep_mode_reg

- TAS2559_VBST_VOLT_REG

Bits D7-D5. Reserved

Bits D4-D3.

0: Over voltage and Over temperature detection output is masked till 100us after ClassD power up
1: Over voltage and Over temperature detection output is masked till 200us after ClassD power up
2: Over voltage and Over temperature detection output is masked till 500us after ClassD power up
3: Over voltage and Over temperature detection output is masked till 1ms after ClassD power up

Bits D2-D0.

0: Max boost voltage = 5.6V for Rev-B
1: Max boost voltage = 6.1V for Rev-B
2: Max boost voltage = 6.6V for Rev-B
3: Max boost voltage = 7.1V for Rev-B
4: Max boost voltage = 7.6V for Rev-B
5: Max boost voltage = 8.1V for Rev-B
6: Max boost voltage = 8.6V for Rev-B
7: Max boost voltage = 9.1V for Rev-B, Don't Use this – NOT RECOMMENDED

4.- TAS2559_SA_CHL_CTRL_REG (B0_P0_R08 - Reserved bits explained below)

D7-D6:

0: Use this Isense gain setting when D2-D1 = 3, Isense Channel full-scale output corresponds to 1.25A
1: Use this Isense gain setting when D2-D1 = 3, Isense Channel full-scale output corresponds to 1.5A
2: Use this Isense gain setting when D2-D1 = 3, Isense Channel full-scale output corresponds to 1.75A
3: Not Supported

D5-D4: Reserved. The register value modification won't have any change.

5. PLL registers are unspecified.

You are right. The PLL coefficients or dividers are not specified yet. So far, we recommend to get the registers configuration from PurePath Console. The datasheet is in process to be updated and this is one of the changes that will be included.

This is all that I could find. I hope this helps you.

Best regards,
Luis Fernando Rodríguez S.

0 Frank Rolsted Jensen over 5 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 140 points

Hi Luis,

Thanks a lot for the answer.

I look forward to have an updated version of the datasheet.

It's not so easy to use the PPC to generate the PLL parameters as it is parameters that are set at runtime.

However, I can do some reverse engineering and make tables with register values for a combination of different mclk/wclk.

Any chance to get a description of following registers ?

#define TAS2559_PLL_P_VAL_REG                   TAS2559_REG(100, 0, 27)
#define TAS2559_PLL_J_VAL_REG                   TAS2559_REG(100, 0, 28)
#define TAS2559_PLL_D_VAL_MSB_REG               TAS2559_REG(100, 0, 29)
#define TAS2559_PLL_D_VAL_LSB_REG               TAS2559_REG(100, 0, 30)
#define TAS2559_PLL_?_VAL_REG               TAS2559_REG(100, 0, 32)

/Frank

0 Luis Fernando Rodriguez S. over 5 years ago in reply to Frank Rolsted Jensen

TI__Guru* 84915 points

Hi, Frank,

These are registers related to the PLL parameters and the N and M dividers.

It seems that the internal PLL is configured through the PLL parameters P, J and D. The master clock or OSC_CLK source is multiplied by the expression:

(J.D) / P.

Notice that D is a decimal value.

P value supports values from 1 to 64. (#define TAS2559_PLL_P_VAL_REG)

D is divided in two registers. Being the register 30 the 8 bits of the LSB (#define TAS2559_PLL_D_VAL_LSB_REG ). And the register 29, the next 6 MSB. (#define TAS2559_PLL_D_VAL_MSB_REG )

J parameter supports values from 1 to 64. (#define TAS2559_PLL_J_VAL_REG )

This PLL configuration allows having a flexible input clock from 1MHz to 20MHz.

Registers 32 and 33 are used to configure the N and M dividers respectively. These dividers reduce the PLL_CLK frequency and its result goes to the DAC_MOD_CLK.

The MSB of registers 32 and 33 is used to power on or power off the dividers. The remaining bits are used to configure the divider from 1 to 127.

Just a recommendation to modify the runtime sequences, you may use the I2C window in PPC to record the registers modification. In that way you will have access to the start up routine and modify the registers as you require.

I hope this helps. Let me know if you have more questions or comments on this.

Best regards,
Luis Fernando Rodríguez S.

0 Frank Rolsted Jensen over 5 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 140 points

Luis,

I think that all I need to know about the registers.

Thanks for an excellent support.

/Frank

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TAS2559: Datasheet: Incomplete register specification