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RTOS: TLV320AIC34 in I2S slave mode device， Noise from recording and playback from the device

user4251816
Prodigy 45 points
Other Parts Discussed in Thread: AM5708

Tool/software: TI-RTOS

I'm using the TLV320AIC34 in the I2S slave mode device, AM5708 built-in DSP as the master device，I drived the AM5708 built-in DSP  outputs the MCLK=22.579MHz, BCLK=1.4412Mhz, WCLK=44.1KHz. Recording and playback are noisy，Noise like a radio. If reg43, reg44 are set to mute, there will be no noise.If the sound input -> PGA -> HPLOUT mode is set, the sound will not be converted by the ADC and DAC, and no noise will appear.If codec is a slave device, is it still necessary to set the internal clock?

reg set below:

{0x00,0x00},
{0x01,0x80},

// codec 作从
{3, 0x00},
{8, 0x00},
{9, 0x00},

// Q value , CLKDIV_IN / (128 × Q) = 22.579MHZ / 128 * 4 = 44.1kHZ, 22.579MHZ is MCLK input

{3, 0x40},

// ADC Init
{102, 0x00},
/* enable the programmable PGA for left and right ADC */
{15, 0x00},
{16, 0x00},

/* MIC3L/R is not connected to the left ADC PGA */
{17, 0xff},

/* MIC3L/R is not connected to the right ADC PGA */
{18, 0xff},

/* power on the Line L1R */
{19, 0x04},

/* power on the Line LIL */
{22, 0x04},

// DAC Init
/* Codec Datapath Setup */
{7, 0x8A},

/* select the DAC L1 R1 Paths */
{41, 0x02},
{42, 0x6c},

/* DAC L to HPLOUT Is connected */
{47, 0x80},
{51, 0x09},
//{46, 0x80},
//{51, 0x09},

/* DAC R to HPROUT is connected */
{64, 0x80},
{65, 0x09},
//{63, 0x80},
//{65, 0x09},

/* DACL1 connected to LINE1 LOUT */
{82, 0x80},
{86, 0x09},

/* DACR1 connected to LINE1 ROUT */
{92, 0x80},
{93, 0x09},
//{94, 0xc6},

/* unmute the DAC */
{43, 0x00},
{44, 0x00},


/* power up the left and right DACs */
{37, 0xE0},

  • 0
    TI__Mastermind 30220 points
    ZDC Z,

    Yes, you must still set the internal clocks.
    The internal clocks do far more than just run the digital audio interface, the clocks also run the DSP engine inside the device and also sets up the over sampling rates. keep in mind that in slave mode, the MCLK,BCLK and WCLK must always be synchronous, because oversampling rates are derived from the MCLK (or BLCK if you choose) then they will also be synchronized.

    A couple questions about your test setup:

    1. You are using the AIC34, so is this configuration for only one Core? or are you running both cores?
    2. are you using the EVM? or is this on your own PCB?
    3. can you capture a screen shot of your BCLK, WCLK and DOUT (from the codec). please get a clean capture by triggering to the WCLK and capturing a single trace. that way I can see the clocks and data clearly. If you capture a 2/3 to 1 full WCLK that is ideal

    best regards,
    -Steve wilson
  • 0 in reply to Steve-Wilson
    Prodigy 45 points

    Thanks for the reply，If codec is a slave device, dsp master device outputs bclk, fclk is the bit clock and frame clock. Why does aic34 also set the internal clock?

    1.Use two cores together。

    2.Own pcb。

  • 0 in reply to user4251816
    TI__Mastermind 30220 points

    user,

    If you are referring to the Fsref setting in Page0 register 7 this relates to AGC time constants, and hpf coefficients when not using the user defined hpf. 

    I await your screen capture.

    best regards,

    -Steve Wilson