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TLV320AIC3106: Need TLV320AIC3106 I2C CFG Review

Wayne Chen (Audio AE)
Genius 15950 points
Part Number: TLV320AIC3106

Hi Sirs,

We are supporting customer to bring up the TLV320AIC3106 with the following clock configuration and signal path:

Suggested BCLK as PLL source:

MCLK = 12.288MHz
BCLK (32*fs) = 512kHz, 1.024MHz, 1.526MHz, 3.072MHz
LRCK (fs) = 16kHz, 32kHz, 48kHz, 96kHz

MCLK = 6.144MHz
BCLK (32*fs) = 256kHz
LRCK (fs) = 8kHz

MCLK = 11.2896MHz 
BCLK (32*fs) = 705.6kHz, 1.4112MHz, 2.8224MHz
LRCK (fs) = 22.05kHz, 44.1kHz, 88.2kHz 

MCLK = 5.6448MHz 
BCLK (32*fs) = 352.8kHz
LRCK (fs) = 11.025kHz

Signal Path:

Right Line Mixer:
Simple mixer control 'TI Right Line Mixer DACL1',0
Simple mixer control 'TI Right Line Mixer DACR1',0
Simple mixer control 'TI Right Line Mixer Line2L Bypass',0
Simple mixer control 'TI Right Line Mixer Line2R Bypass',0
Simple mixer control 'TI Right Line Mixer PGAL Bypass',0
Simple mixer control 'TI Right Line Mixer PGAR Bypass',0

Mono Mixer:

Simple mixer control 'TI Mono Mixer DACL1',0
Simple mixer control 'TI Mono Mixer DACR1',0
Simple mixer control 'TI Mono Mixer Line2L Bypass',0
Simple mixer control 'TI Mono Mixer Line2R Bypass',0
Simple mixer control 'TI Mono Mixer PGAL Bypass',0
Simple mixer control 'TI Mono Mixer PGAR Bypass',0

Because the AIC3106 GUI is not compatible with Windows 10 OS, hence we are not able to test I2C coding on the EVM.
Would you please assist us to point out missing or mistake with the I2C configurations we captured on customer's system board (The CFG is not functional now)?

We can send schematic by Email:

Configurations during power up:
-----------------------------------------


w 36 00 00
w 36 01 00
w 36 02 00
w 36 03 91
w 36 04 80
w 36 05 00
w 36 06 00
w 36 07 0a
w 36 08 00
w 36 09 00
w 36 0a 00
w 36 0b 01
w 36 0c 00
w 36 0d 00
w 36 0e 00
w 36 0f 80
w 36 10 80
w 36 11 ff
w 36 12 ff
w 36 13 78
w 36 14 78
w 36 15 78
w 36 16 78
w 36 17 78
w 36 18 78
w 36 19 00
w 36 1a 00
w 36 1b fe
w 36 1c 00
w 36 1d 00
w 36 1e fe
w 36 1f 00
w 36 20 18
w 36 21 18
w 36 22 00
w 36 23 00
w 36 24 00
w 36 25 c0
w 36 26 00
w 36 27 00
w 36 28 00
w 36 29 50
w 36 2a 00
w 36 2b 00
w 36 2c 80
w 36 2d 00
w 36 2e 00
w 36 2f 00
w 36 30 00
w 36 31 00
w 36 32 00
w 36 33 04
w 36 34 00
w 36 35 00
w 36 36 00
w 36 37 00
w 36 38 00
w 36 39 00
w 36 3a 04
w 36 3b 00
w 36 3c 00
w 36 3d 00
w 36 3e 00
w 36 3f 00
w 36 40 00
w 36 41 04
w 36 42 00
w 36 43 00
w 36 44 00
w 36 45 00
w 36 46 00
w 36 47 00
w 36 48 04
w 36 49 00
w 36 4a 00
w 36 4b 00
w 36 4c 00
w 36 4d 00
w 36 4e 00
w 36 4f 00
w 36 50 00
w 36 51 00
w 36 52 00
w 36 53 00
w 36 54 00
w 36 55 00
w 36 56 00
w 36 57 00
w 36 58 00
w 36 59 00
w 36 5a 00
w 36 5b 00
w 36 5c 00
w 36 5d 00
w 36 5e 00
w 36 5f 00
w 36 60 00
w 36 61 00
w 36 62 00
w 36 63 00
w 36 64 00
w 36 65 00
w 36 66 02
w 36 67 00
w 36 68 00
w 36 69 00
w 36 6a 00
w 36 6b 00
w 36 6c 00
w 36 6d 00

-----------------------------------------

Playback, All Path ON
-----------------------------------------
w 36 07 8a
w 36 0f 76
w 36 10 76
w 36 13 00
w 36 14 00
w 36 15 00
w 36 16 00
w 36 17 00
w 36 18 00
w 36 19 80
w 36 2b af
w 36 2c af
w 36 2d 2f
w 36 2e 2f
w 36 2f af
w 36 33 0c
w 36 34 2f
w 36 35 2f
w 36 36 af
w 36 3a 0c
w 36 3e 2f
w 36 3f 2f
w 36 40 af
w 36 41 0c
w 36 45 2f
w 36 46 2f
w 36 47 af
w 36 48 0c
w 36 49 2f
w 36 4a 2f
w 36 4b af
w 36 4c 2f
w 36 4d 2f
w 36 4e af
w 36 4f 08
w 36 50 2f
w 36 51 2f
w 36 52 af
w 36 55 80
w 36 56 08
w 36 5a 2f
w 36 5b 2f
w 36 5c af
w 36 5d 08
w 36 65 01
w 36 05 00
w 36 06 00
w 36 25 c0
w 36 33 0d
w 36 3a 0d
w 36 41 0d
w 36 48 0d
w 36 56 09
w 36 2b 2f
w 36 2c 2f
w 36 0a 00
w 36 2b 2f
w 36 2c 2f
-----------------------------------------


If you have any question, please do not hesitate to inform us.

Wayne Chen
06/03/2019

  • 0
    TI__Mastermind 30210 points
    Wayne,

    It isn't at all clear what you are trying to do here.

    you've told me that the suggested PLL input clock is BCLK, but you listed 5 different frequencies,



    Most of your Configurations during power up are the default register value, but the ones that are not:

    w 36 03 91 # PLL on, P = 1
    w 36 04 80 # J = 32
    w 36 05 00 # D val =0
    w 36 06 00 # D VAL = 0
    w 36 07 0a # Fs ref= 44.1k, no dual rate mode, L->L R->R
    w 36 08 00 # Slave mode,
    w 36 09 00 # I2S mode, 16 bit
    w 36 0b 01 # R Val = 1
    w 36 25 c0 # power up DACs

    Suggest that you are using a 3.072Mhz PLL_IN clock, (although you need to set register 7 to 0x80) which i assume would be coming from the BLCK, but you don't set register 102 that way.

    but your second configuration sets the codec_clk_in as the CLK dividers, so... not sure why you're powering up the PLL?

    Also, in your second configuration you are setting the PGAs to their highest gain setting, which I do not recommend,

    You don't end up routing the Line2R,Line2L, PGAL or PGAR signals to the output mixers, but the Right and LEFT DACs are routed, however.. you set the LEFT and Right DAC volume to -23.5, and then you set the Mixer volume to -23.5 so you attenuate the DACs significantly.


    Can you explain exactly what you are trying to do?

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    TI__Genius 15950 points
    Hello Wilson,

    Thank you for your advise. The I2C instructions we listed above were captured from customer's system board during power up and playback by an logic analyzer, and I converted them into TI's CFG format for trouble shooting.

    Here we need your recommendations to polish the CFG to support customer's clock configurations. Can we use a single CFG to support all of customer's 32*fs clock configurations?

    We will double check signal path and gain setting once we can solve clock configuration mistakes.

    Thank you and Best regards,

    Wayne Chen
    06/03/2019
  • 0 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 30210 points
    Wayne,

    No, the register configuration will have to change depending on the sampling rate.

    I can create a configuration, can I assume MCLK = 12.288 Mhz?

    what format does the customer prefer? I can provide them a .csv if that is more helpful to them.

    -Steve Wilson
  • 0 in reply to Steve-Wilson
    TI__Genius 15950 points

    Hello Wilson,

    Thanks for your great supporting, Customer has four clock configurations. Would you please assist us to generate four CFGs for system integration?
    Nice to have a CSV to generate AIC3106 configurations because the EVM GUI is malfunction in Windows 10.

    MCLK = 12.288MHz 
    BCLK (32*fs) = 512kHz, 1.024MHz, 1.526MHz, 3.072MHz
    LRCK (fs) = 16kHz, 32kHz, 48kHz, 96kHz

    MCLK = 6.144MHz 
    BCLK (32*fs) = 256kHz
    LRCK (fs) = 8kHz

    MCLK = 11.2896MHz 
    BCLK (32*fs) = 705.6kHz, 1.4112MHz, 2.8224MHz
    LRCK (fs) = 22.05kHz, 44.1kHz, 88.2kHz 

    MCLK = 5.6448MHz 
    BCLK (32*fs) = 352.8kHz
    LRCK (fs) = 11.025kHz

    We also found customer's Linux driver is problematic. I will send customer's source code to you by Email.

    Thank you and Best regards,

    Wayne Chen
    06/04/2019

      

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 30210 points
    Wayne,

    Yes, we hope to address the Windows 10 compatibility issue soon.

    They will need to have slightly different clock configurations for each of these.

    for the MCLk = 12.288.11.2896 Mhz variants the general clock setup is like so:

    0x00,0x00
    0x01,0x00
    0x02,0x00 # make 0x44 for 16k, make 0x11 for 32khz, Make 0x22 for 22.05khz
    0x03,0x10
    0x04,0x04
    0x05,0x00
    0x06,0x00
    0x07,0x0a # make 0x6a for 96 0xea for 88khz
    0x08,0x00
    0x09,0x00
    0x0a,0x00
    0x65,0x01


    For MCLK = 5.6448/6/144Mhz

    0x00,0x00
    0x01,0x00
    0x02,0xaa # make 0x66 for 11.025khz
    0x03,0x10
    0x04,0x20
    0x05,0x00
    0x06,0x00
    0x07,0x0a #make 0x8a for 11.025khz
    0x08,0x00
    0x09,0x00
    0x0a,0x00
    0x65,0x00

    best regards,
    -STeve Wilson
  • 0 in reply to Steve-Wilson
    TI__Genius 15950 points
    Hello Wilson,

    We will collaborate with customer to implement clock configurations and keep you updated of our test result.

    Wayne Chen
    06/04/2019
  • 0 in reply to Wayne Chen (Audio AE)
    TI__Genius 15950 points

    Hello Steve,

    Customer is updating Linux driver based on your recommendations. Here we have some questions need your suggestions:

    1. Do we need to keep MCLK all the way?
    2. We are testing 44.1kHz sample rate with 11.2896MHz MCLK. The system sends the following instructions during power up:

    w 36 07 0a
    w 36 0f 77
    w 36 10 77
    w 36 13 00
    w 36 14 00
    w 36 16 00
    w 36 19 80
    w 36 2b a8
    w 36 2c a8
    w 36 2d 2f
    w 36 2e 2f
    w 36 2f af
    w 36 33 0c
    w 36 34 2f
    w 36 35 2f
    w 36 36 af
    w 36 3a 0c
    w 36 3e 2f
    w 36 3f 2f
    w 36 40 af
    w 36 41 0c
    w 36 45 2f
    w 36 46 2f
    w 36 47 af
    w 36 48 0c
    w 36 49 2f
    w 36 4a 2f
    w 36 4b af
    w 36 4c 2f
    w 36 4d 2f
    w 36 4e af
    w 36 4f 08
    w 36 50 2f
    w 36 51 2f
    w 36 52 af
    w 36 56 08
    w 36 5a 2f
    w 36 5b 2f
    w 36 5c af
    w 36 5d 08
    w 36 65 01
    w 36 05 00
    w 36 06 00
    w 36 25 c0
    w 36 33 0d
    w 36 3a 0d
    w 36 41 0d
    w 36 48 0d
    w 36 56 09
    w 36 2b 28
    w 36 2c 28

    Memory dump data is in line with your recommendations for clocking. However, there is no sound with LINE2L input to HPLOUT & HPLCOM. Would you please assist us to check if there are missing or mistake? 

    r 36 00 01 # Returned 0x00
    r 36 01 01 # Returned 0x00
    r 36 02 01 # Returned 0x00
    r 36 03 01 # Returned 0x10
    r 36 04 01 # Returned 0x04
    r 36 05 01 # Returned 0x00
    r 36 06 01 # Returned 0x00
    r 36 07 01 # Returned 0x0a
    r 36 08 01 # Returned 0x00
    r 36 09 01 # Returned 0x00
    r 36 0a 01 # Returned 0x00

    r 36 0b 01 # Returned 0x01
    r 36 0c 01 # Returned 0x00
    r 36 0d 01 # Returned 0x00
    r 36 0e 01 # Returned 0x00
    r 36 0f 01 # Returned 0x77
    r 36 10 01 # Returned 0x77
    r 36 11 01 # Returned 0xff
    r 36 12 01 # Returned 0xff
    r 36 13 01 # Returned 0x00
    r 36 14 01 # Returned 0x00
    r 36 15 01 # Returned 0x78
    r 36 16 01 # Returned 0x00
    r 36 17 01 # Returned 0x78
    r 36 18 01 # Returned 0x78
    r 36 19 01 # Returned 0x86
    r 36 1a 01 # Returned 0x00
    r 36 1b 01 # Returned 0xfe
    r 36 1c 01 # Returned 0x00
    r 36 1d 01 # Returned 0x00
    r 36 1e 01 # Returned 0xfe
    r 36 1f 01 # Returned 0x00
    r 36 20 01 # Returned 0x00
    r 36 21 01 # Returned 0x00
    r 36 22 01 # Returned 0x00
    r 36 23 01 # Returned 0x00
    r 36 24 01 # Returned 0x00
    r 36 25 01 # Returned 0xc0
    r 36 26 01 # Returned 0x00
    r 36 27 01 # Returned 0x00
    r 36 28 01 # Returned 0x00
    r 36 29 01 # Returned 0x00
    r 36 2a 01 # Returned 0x00
    r 36 2b 01 # Returned 0x28
    r 36 2c 01 # Returned 0x28
    r 36 2d 01 # Returned 0x2f
    r 36 2e 01 # Returned 0x2f
    r 36 2f 01 # Returned 0xaf
    r 36 30 01 # Returned 0x00
    r 36 31 01 # Returned 0x00
    r 36 32 01 # Returned 0x00
    r 36 33 01 # Returned 0x0f
    r 36 34 01 # Returned 0x2f
    r 36 35 01 # Returned 0x2f
    r 36 36 01 # Returned 0xaf
    r 36 37 01 # Returned 0x00
    r 36 38 01 # Returned 0x00
    r 36 39 01 # Returned 0x00
    r 36 3a 01 # Returned 0x0f
    r 36 3b 01 # Returned 0x00
    r 36 3c 01 # Returned 0x00
    r 36 3d 01 # Returned 0x00
    r 36 3e 01 # Returned 0x2f
    r 36 3f 01 # Returned 0x2f
    r 36 40 01 # Returned 0xaf
    r 36 41 01 # Returned 0x0f
    r 36 42 01 # Returned 0x00
    r 36 43 01 # Returned 0x00
    r 36 44 01 # Returned 0x00
    r 36 45 01 # Returned 0x2f
    r 36 46 01 # Returned 0x2f
    r 36 47 01 # Returned 0xaf
    r 36 48 01 # Returned 0x0f
    r 36 49 01 # Returned 0x2f
    r 36 4a 01 # Returned 0x2f
    r 36 4b 01 # Returned 0xaf
    r 36 4c 01 # Returned 0x2f
    r 36 4d 01 # Returned 0x2f
    r 36 4e 01 # Returned 0xaf
    r 36 4f 01 # Returned 0x08
    r 36 50 01 # Returned 0x2f
    r 36 51 01 # Returned 0x2f
    r 36 52 01 # Returned 0xaf
    r 36 53 01 # Returned 0x00
    r 36 54 01 # Returned 0x00
    r 36 55 01 # Returned 0x00
    r 36 56 01 # Returned 0x0b
    r 36 57 01 # Returned 0x00
    r 36 58 01 # Returned 0x00
    r 36 59 01 # Returned 0x00
    r 36 5a 01 # Returned 0x2f
    r 36 5b 01 # Returned 0x2f
    r 36 5c 01 # Returned 0xaf
    r 36 5d 01 # Returned 0x08
    r 36 5e 01 # Returned 0xd6
    r 36 5f 01 # Returned 0x0c
    r 36 60 01 # Returned 0x00
    r 36 61 01 # Returned 0x00
    r 36 62 01 # Returned 0x00
    r 36 63 01 # Returned 0x00
    r 36 64 01 # Returned 0x00

    r 36 65 01 # Returned 0xc1

    r 36 66 01 # Returned 0x02
    r 36 67 01 # Returned 0x00
    r 36 68 01 # Returned 0x00
    r 36 69 01 # Returned 0x00
    r 36 6a 01 # Returned 0x00
    r 36 6b 01 # Returned 0x00
    r 36 6c 01 # Returned 0x00
    r 36 6d 01 # Returned 0x00
    r 36 6e 01 # Returned 0x00
    r 36 6f 01 # Returned 0x00
    r 36 70 01 # Returned 0x00
    r 36 71 01 # Returned 0x00
    r 36 72 01 # Returned 0x00
    r 36 73 01 # Returned 0x00
    r 36 74 01 # Returned 0x00
    r 36 75 01 # Returned 0x00
    r 36 76 01 # Returned 0x00
    r 36 77 01 # Returned 0x00
    r 36 78 01 # Returned 0x00
    r 36 79 01 # Returned 0x00
    r 36 7a 01 # Returned 0x00
    r 36 7b 01 # Returned 0x00
    r 36 7c 01 # Returned 0x00
    r 36 7d 01 # Returned 0x00
    r 36 7e 01 # Returned 0x00
    r 36 7f 01 # Returned 0x00
    r 36 80 01 # Returned 0x00
    r 36 81 01 # Returned 0x00
    r 36 82 01 # Returned 0x00
    r 36 83 01 # Returned 0x10
    r 36 84 01 # Returned 0x04
    r 36 85 01 # Returned 0x00
    r 36 86 01 # Returned 0x00
    r 36 87 01 # Returned 0x0a
    r 36 88 01 # Returned 0x00
    r 36 89 01 # Returned 0x00
    r 36 8a 01 # Returned 0x00
    r 36 8b 01 # Returned 0x01
    r 36 8c 01 # Returned 0x00
    r 36 8d 01 # Returned 0x00
    r 36 8e 01 # Returned 0x00
    r 36 8f 01 # Returned 0x77
    r 36 90 01 # Returned 0x77
    r 36 91 01 # Returned 0xff
    r 36 92 01 # Returned 0xff
    r 36 93 01 # Returned 0x00
    r 36 94 01 # Returned 0x00
    r 36 95 01 # Returned 0x78
    r 36 96 01 # Returned 0x00
    r 36 97 01 # Returned 0x78
    r 36 98 01 # Returned 0x78
    r 36 99 01 # Returned 0x86
    r 36 9a 01 # Returned 0x00
    r 36 9b 01 # Returned 0xfe
    r 36 9c 01 # Returned 0x00
    r 36 9d 01 # Returned 0x00
    r 36 9e 01 # Returned 0xfe
    r 36 9f 01 # Returned 0x00
    r 36 a0 01 # Returned 0x00
    r 36 a1 01 # Returned 0x00
    r 36 a2 01 # Returned 0x00
    r 36 a3 01 # Returned 0x00
    r 36 a4 01 # Returned 0x00
    r 36 a5 01 # Returned 0xc0
    r 36 a6 01 # Returned 0x00
    r 36 a7 01 # Returned 0x00
    r 36 a8 01 # Returned 0x00
    r 36 a9 01 # Returned 0x00
    r 36 aa 01 # Returned 0x00
    r 36 ab 01 # Returned 0x28
    r 36 ac 01 # Returned 0x28
    r 36 ad 01 # Returned 0x2f
    r 36 ae 01 # Returned 0x2f
    r 36 af 01 # Returned 0xaf
    r 36 b0 01 # Returned 0x00
    r 36 b1 01 # Returned 0x00
    r 36 b2 01 # Returned 0x00
    r 36 b3 01 # Returned 0x0f
    r 36 b4 01 # Returned 0x2f
    r 36 b5 01 # Returned 0x2f
    r 36 b6 01 # Returned 0xaf
    r 36 b7 01 # Returned 0x00
    r 36 b8 01 # Returned 0x00
    r 36 b9 01 # Returned 0x00
    r 36 ba 01 # Returned 0x0f
    r 36 bb 01 # Returned 0x00
    r 36 bc 01 # Returned 0x00
    r 36 bd 01 # Returned 0x00
    r 36 be 01 # Returned 0x2f
    r 36 bf 01 # Returned 0x2f
    r 36 c0 01 # Returned 0xaf
    r 36 c1 01 # Returned 0x0f
    r 36 c2 01 # Returned 0x00
    r 36 c3 01 # Returned 0x00
    r 36 c4 01 # Returned 0x00
    r 36 c5 01 # Returned 0x2f
    r 36 c6 01 # Returned 0x2f
    r 36 c7 01 # Returned 0xaf
    r 36 c8 01 # Returned 0x0f
    r 36 c9 01 # Returned 0x2f
    r 36 ca 01 # Returned 0x2f
    r 36 cb 01 # Returned 0xaf
    r 36 cc 01 # Returned 0x2f
    r 36 cd 01 # Returned 0x2f
    r 36 ce 01 # Returned 0xaf
    r 36 cf 01 # Returned 0x08
    r 36 d0 01 # Returned 0x2f
    r 36 d1 01 # Returned 0x2f
    r 36 d2 01 # Returned 0xaf
    r 36 d3 01 # Returned 0x00
    r 36 d4 01 # Returned 0x00
    r 36 d5 01 # Returned 0x00
    r 36 d6 01 # Returned 0x0b
    r 36 d7 01 # Returned 0x00
    r 36 d8 01 # Returned 0x00
    r 36 d9 01 # Returned 0x00
    r 36 da 01 # Returned 0x2f
    r 36 db 01 # Returned 0x2f
    r 36 dc 01 # Returned 0xaf
    r 36 dd 01 # Returned 0x08
    r 36 de 01 # Returned 0xd6
    r 36 df 01 # Returned 0x0c
    r 36 e0 01 # Returned 0x00
    r 36 e1 01 # Returned 0x00
    r 36 e2 01 # Returned 0x00
    r 36 e3 01 # Returned 0x00
    r 36 e4 01 # Returned 0x00
    r 36 e5 01 # Returned 0xc1
    r 36 e6 01 # Returned 0x02
    r 36 e7 01 # Returned 0x00
    r 36 e8 01 # Returned 0x00
    r 36 e9 01 # Returned 0x00
    r 36 ea 01 # Returned 0x00
    r 36 eb 01 # Returned 0x00
    r 36 ec 01 # Returned 0x00
    r 36 ed 01 # Returned 0x00
    r 36 ee 01 # Returned 0x00
    r 36 ef 01 # Returned 0x00
    r 36 f0 01 # Returned 0x00
    r 36 f1 01 # Returned 0x00
    r 36 f2 01 # Returned 0x00
    r 36 f3 01 # Returned 0x00
    r 36 f4 01 # Returned 0x00
    r 36 f5 01 # Returned 0x00
    r 36 f6 01 # Returned 0x00
    r 36 f7 01 # Returned 0x00
    r 36 f8 01 # Returned 0x00
    r 36 f9 01 # Returned 0x00
    r 36 fa 01 # Returned 0x00
    r 36 fb 01 # Returned 0x00
    r 36 fc 01 # Returned 0x00
    r 36 fd 01 # Returned 0x00
    r 36 fe 01 # Returned 0x00
    r 36 ff 01 # Returned 0x00

    Thank you and Best regards,

    Wayne Chen
    06/05/2019

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 30210 points

    Wayne, 

    1. Please clarify.  What do you mean "keep MCLK all the way"?  do you mean keep it constant? keep it running?  

    2. if you want to use the Line2 Bypass path, you must program register 40 (bits D2-D5)  right now these are set to 0,  meaning the bypass path is disabled. 

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    TI__Genius 15950 points

    Hi Steve,

    Thanks for your concern.

    1. Customer's SOC can send MCLK when music stream startup, and turn off MCLK when music stream stopped. Do we need to reprogram the AIC3106 after MCLK power cycling? Should we keep MCLK always on to reduce software effort?
    2. Thank you for your advise. We will test it and get you back shortly.

    Thank you and Best regards,

    Wayne Chen
    06/05/2019

       

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Genius 15950 points

    Hello Wilson,

    Thanks for supporting. The loopback path is functional with register 0x2d = 0x80. However, we are not able to play sound from CPU. We are checking CPU's I2S format and will need tips of customer's signal path configurations.




    Thank you and Best regards,

    Wayne Chen
    06/06/2019

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 30210 points

    Wayne,

    1. The MCLK does play a role in some of the important features of the AIC3106,  such as the pop suppression and soft stepping. so it does help to provide thisclock constantly.  The AIC3106 should have the DAC and ADC powered down when changing the MCLK frequency and sample rate (and programming the associated registers)

    2.  sounds good,  Thank you for your work Wayne.

    best regards,

    -Steve Wilson

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 30210 points

    Hi Wayne, 

    The line2L bypass will only work once register 40 is also configured.

    best regards,

    -STeve Wilson