TAS2557: Noise when using low sample rates

Hi Viktor,

In order to configure the device to 22.05kHz sample rate some registers that are not currently shown in the datasheet must be changed. Usually these registers are calculated within PPC3, but as 22.05kHz is not one of the options this must be made manually.
Let me create and test a script for this configuration and I'll share it with you.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

That would be great!
Thank you, Ivan.

/Viktor

Hi Viktor,

22.05kHz sample rate is not supported on this device, as you can see in Book 0, Page 0, Register 0x2F (Table 50).
The supported sample rates are 8k, 16k, 48k and 96kHz.

Do you want to use the device in tuning mode? You can configure the device to any of these sampling rates using PPC3 end system integration panel.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

I also noticed that in ROM Mode 1/2, PPC3 end system integration only support 44.1k and 48k.
Is there any settings that I need to apply besides WDIV and BDIV ratio to make the device support 22050Hz?

It seems most logical that you can choose 44.1k or 48k with PPC3 and then use some divider to use a multiple of that sample rate for the device. Because the datasheet states that in ROM Mode the device supports sample rates from 8kHz - 96kHz, with a maximum of 48kHz when using speaker protection.

/Viktor

Viktor,

The clock dividers might be able to set 22050Hz, but Register 0x2F from Book 0, Page 0 does not have this sample rate as an option.

ROM mode supports lower sample rates, same as Tuning mode, even though PPC3 only shows 48k and 44.1k options. If you need 8k or 16k rates in ROM mode please let us know and I can provide a cfg file for these rates and your specific source clock.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Ivan,

I tried configuring the device for 48kHz/16bit and played a 48kHz/16bit audio file and the sound was clear and crisp.
Then i tried to configure the device for 16kHz/16bit, changing register 0x2F as well as changing the BDIV/WDIV to the correct frequencies, and played a 16kHz/16bit sound file. The sound was just as noisy and unclear as it was when i played using 22.05kHz/16bit.

So is there nothing else than changing register 0x2F and BDIV/WDIV?

I compared the configuration files between 44.1kHz/48kHz and noticed that there are some changes in registers not shown in the TAS2557 datasheet:
1) Book: 0x64, Page: 0x00, register: 0x1c 
2) Book: 0x64, Page: 0x00, register: 0x1d
3) Book: 0x64, Page: 0x00, register: 0x1e
4) Book: 0x00, Page: 0x32, register: 0x54 - 0x57

Do you have any documentation regarding these registers?

I also noticed an existing thread regarding my problem which sadly has been locked due to inactivity by the poster, but would be interesting to get an answer to:
https://e2e.ti.com/support/audio/f/6/t/718459?TAS2557-Asking-for-the-TAS2557-sampling-rate-support

Thank you Ivan,
/Viktor

Viktor,

The clock source goes through some divider/multiplying stages, additional to register 0x2F.

1) Book: 0x64, Page: 0x00, register: 0x1c                  PLL J multiplier
2) Book: 0x64, Page: 0x00, register: 0x1d                  PLL D multiplier (MSB)
3) Book: 0x64, Page: 0x00, register: 0x1e                  PLL D multiplier (LSB)
4) Book: 0x00, Page: 0x32, register: 0x54 - 0x57       This book and page correspond to the program memory

Currently there is no public documentation that shows further detail on device clock configuration, but in the meantime you can provide the following details and we can send back a cfg file:

• Clock source: BCLK or MCLK
• Clock source frequency: Same as options shown in PPC3 for BCLK or MCLK
• Sampling frequency: 8k, 16k, 48k, (96k just for ROM modes)
• Mode: ROM1, ROM2, Tuning

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Okay, thank you!

Clock source: MCLK
Clock source freq: 12MHz
Sampling freq: 16k
Mode: ROM1
Also, we are using I2S where TAS2557 is master, thus generating BCLK and WCLK.

If possible, could you please create a cfg-file for both 16k and 8k sampling frequency?

/Viktor

Hi Viktor,

Attached is a script that should work for the following:

• MCLK = 12MHz input clock
• Sampling rate 16kHz
• ROM Mode 1
• Master (BCLK and WCLK as outputs, derived from MCLK)

Could you please try this on your side? Currently I'm not able to test with a MCLK = 12MHz that can send 16kHz sample rate data. Although I'll try this as soon as possible.

If this works fine, then I can provide 8k cfg as well.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

48k_12M_MCLK_ROM1_Master.cfg

Hi Viktor,

Did you got a chance to test the attached script on your side?

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators