TLV320AIC3105: 24 bits 96Khz Slave mode

Dear all
I'm using the TLV320AIC3105 in a 24bits 96Khz project.
The Codec is configured in slave mode, not using internal PLL.

When configured in 24b/96Hz, my MCU generates a MCLK of 36,864MHz (384 FS).
I enabled the CODEC in dual rate mode to support 96KHz.
I plan to set PLL Q = 6 so the resulting Fs(ref) is MCLK / (128xQ) = 36,864MHz / (768) = 48K

BUT

I read in the datasheet page 28 :

The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is enabled in the DAC.
Allowed Q values = 4, 8, 9, 12, 16

So what is the correct setup to support 24/96 with a MCLK @ 384Fs ? 

Thanks