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TLV320AIC3104: setting up the internal closck

ajayt
Genius 9555 points
Part Number: TLV320AIC3104


Hi,  I have a MCLK of 12MHZ and incoming data on I2S at 16KHz sample rate (fs).  What would the recommended clock tree look like?

Do I have to create an internal clock that is 256 x Fs   ie  4.096MHz DAC  ie DAC fs.   To get the 4.096Mhz I have to use the PLL as there is not an integer solution. 

Can I also ask what the DAC sample rate register does ( page 1 reg 02)  in my case is this changing the Fs 0f 16KZ to a lower value that I then have to multiply by 256 to get the correct DAC Fs. 

audioclock.docx

  • 0
    TI__Mastermind 30220 points

    Hi Alan, 

    I saw you Emailed me as well, I apologize for my delayed response, I've been in meetings all morning. 

    Codec_CLK must always = 256*Fsref.   and Fsref can only be 48k or 44.1k.   So on the AIc310x devices this must be 12.288Mhz or 11.2896Mhz (48/44.1)

    register 2 automatically configures the N and M dividers to give you the proper AOSR for each sampling rate. 

    there are two issues here. 

    1. if they are using an MCLK of 12Mhz,  there is no possible way this could be synchronous with the WCLK and BCLK.  which is problematic for reasons we've already discussed

    2. their Fsref will not be 48khz,  it will be 46.875kHz.  This also means that the ADC and DAC will be running at 15.625Khz,  So not only are the clocks not synchronous, they are effectively running the DAC at a different frequency than they are running their audio clocks at. 

    We can at least try the PLL to see if the noise is improved by providing the same frequency clock (just not synchronous) 

    use the settings below:

    reg 3 = 0x91

    reg 4 = 0x20

    reg 5 = 0x17

    reg 6 = 0x00

    reg 101 = 0x 00

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    TI__Genius 9555 points

    Hi 

    I need to get back in touch with you again as we have another issue with the PLL setup that we previously thought was ok.

     

    For my last fix I set up the PLL as per the last email for 8MHz clock and 7800Hz sample rate and 12MHz clock 15600Hz sample rate and Fs(ref) was 46800Hz. It seemed to work fine and the audio sounded ok with both settings.

     

    The problem I have now is when we play a continuous 1KHz tone on the 15600Hz channel it sounds like samples are being dropped and there is a slight clicking heard at regular intervals when the tone is playing.

     

    I tried to modify the code so we could switch between PLLDIV_OUT and CLKDIV_OUT but the system does not like this.

     

    1. Is it ok to switch between these two paths?
    2. Would we expect to drop samples with the setting were using and the PLL error or-2.5%?

  • 0 in reply to ajayt
    TI__Mastermind 30220 points

    Alan, 

    1. it is ok to switch between the paths,  but not dynamically.  The ADC and DACs should be powered down,  then clock path switched,  then ADC and DAC turned back on. 

    2.  I would not expect the dropped samples,  can you send a recording?  maybe a screen shot of the digital audio clocks and data?

    best regards,

    -Steve Wilson