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PCM1690: I2S TDM: single rate or dual rate ?

Part Number: PCM1690
Other Parts Discussed in Thread: PCM1681

I'm controlling the DAC via SPI serial control mode (software control). Fs = 44.1KHz. The external audio sync signals, drived to the DAC are: SCKI =11.2896MHz (rate=256xFs); BCK=11.2896MHz (rat =256xFs); LRCK = 44.1KHz (single positive pulse at the start of the frame, changing on the falling edge of BCK). The TDM audio data are on DIN1, changing on the falling edge of BCK. AMUTEI is tied to +3.3V, the external reset is released (go high) when all the audio sync are stable, the SPI writings start later. So I tried with minimum registers programming, keeping most registers at the default state. For example:

Hex 41 ->  Hex 08 which means "Power-save enable mode", "24-bit high-speed I2S TDM format" (because of DIN1).

Because all other registers are at default values, it should be: dual rate (auto selection), audio data applied to DIN1 pin (see 7.4.2 "Audio Data Interface Formats and Timing", and Table 5 of datasheet), no muting applied to any analog outputs, no attenuation applied to any analog output, normal operation for DAC[1:8]. Unfortunately, no audio signal is generated by the DAC.

So I tried:

Hex 41 ->  Hex 88 which means "Power-save disable mode", 24-bit high-speed I2S TDM format. No audio signal is generated by the DAC.

So I tried:

Hex 40 -> Hex C1 which means "single rate" +  Hex 41 -> Hex 06 which means Power-save enable mode (default), 24-bit I2S TDM format. Nothing (resync does not work moreover).

The question is: does the single sampling mode, with SCKI=256xFs, only DIN1 used, and I2S TDM format work or not ? Which is the right configuration I should use?

  • Hi Stefano,

    First, I do not think you need to use the high-speed TDM mode.  You should write to register 0x41 the value 0x06 to use the standard I2S TDM mode.  Register 0x40 can be left as default. 

    You should also confirm the following:

    1. Using a digital analyzer or scope - is the I2S data valid and as expected.

    2. Using a digital analyzer or scope - is the SPI frame valid and expected?

    3. Measure the voltages on VCC1, VCC2, VCOM.

    Can you share a schematic?

    Thanks,

    Paul

  • Hi Paul.

    First of all thank you for your quick reply. Now:

    1) The TDM I2S data are valid. Audio data and sync are generated by the same DSP previously connected to a PCM1681 DAC, with parallel hardware control: 24-bits I2S mode TDM format selected (FMT1=high, FMT0=high). In this case everything works fine. Moreover I checked again using my scope: the audio stream (data and sync) are OK. On the other hand, the DSP has not changed, so...

    2) I checked the SPI frame using the scope, and the SPI frame seems to be correct: the SPI data change on the falling edge of the SPI clock, so the SPI clock can sample the data on the rising edge. Moreover the DAC reset is released after audio sync are stable, and same for the first SPI writing. But I noticed that changing the power save status (enabled/disabled), DAC outputs change from GNDA to VCOM: shouldn't this only happen if the DACs are in stop condition (disabled)? I will try to reactivate the DACs.

    3) VCC1, VCC2, VCOM are right.

    Thanks,

    Stefano10.pdf

  • Hi Stefano,

    I am surprised that the output are GND after startup.  

    Can you share a screenshot of the SPI frame?

    Thanks,

    Paul

  • Any updates?

  • Hi Paul.

    Sorry for my late response. Below the activity report that solved the problem:

    1) I semplified the gating of SPI clock and data towards the DAC (see the attachment). The gating is  necessary in my application because the Cortex SPI port is shared, and I want to avoid any unnecessary activity towards the DAC.

    2) I replaced the DSP module in my system (probably something didn't work properly).

    3) I have written only 0x06 to the 0x41 register (as you suggested).

    After that everything started to work properly!

    Thanks for the support!

    Stefano

    PCM1690.pdf