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Generating I2S master clocks without a master device

Noel Neu
Prodigy 55 points

Other Parts Discussed in Thread: TLV320DAC3203

Hi !

I am looking for a way to generate LRCLK and BCLK signals in order to connect two I2S slaves.

So far, I have always had some chip capable of operation in master mode; not this time however.

I could imagine using a clock divider to generate BCLK and LRCLK from MCLK, but im wondering if there is a better method.

How is this usually handled ? Is there an IC suited for this task ?

Thanks in advance !

Noel

  • 0
    TI__Genius 12705 points

    Hello Noel,

    I will transfer this to audio forum which likely can answer your query.

    Kind Regards,

  • 0
    TI__Guru** 114505 points

    Hi Noel,

    Welcome to e2e.

    Can you provide further details about your application?
    From the audio applications perspective, most of our digital interface devices can be configured as Master, generating WCLK and BCLK from MCLK. 

    What is your audio source? Perhaps using one of these devices could help you reduce your part count. These devices can be configured as Master, but still receive data from a host device on DIN.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators

  • 0 in reply to Ivan Salazar
    Prodigy 55 points

    Hi Ivan,

    thanks for your reply !

    The source is a third party embedded streaming solution based on an ARM processor. It is operating in slave mode. It gives information about the sample rate to the uC via UART.

    The DAC chip should be the AKM4493, as it has excellent audio performance. It cannot operate in i2s master mode.

    Part count and price is not really an issue here; rather performance.

    If in any way possible, I would like to stick to that DAC chip, since it is already used in other designs which do have a DSP acting as master. 

    I was wondering If there is such thing as a master only IC that would provide LRCLK and BCLK to both devices; but not data.

    Thanks for your suggestions!

    Noel

  • 0 in reply to Noel Neu
    TI__Guru** 114505 points

    Noel,

    So if I understand correctly, both your host and DAC are slave only, correct?

    Never tried something like this, but I think it should work:

    • Configure one of our DACs (like TLV320DAC3203) as Master, and provide MCLK. Using the PLL you can generate BCLK and WCLK clocks.
    • Connect BCLK and WCLK from our DAC to your Host and DAC, using the same sampling frequency
    • TLV320DAC3203 can provide the clocks, without sending/receiving any data, while the other two slaves send data to each other.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators