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TAS2505: TAS2505 drvier

Part Number: TAS2505


Dear Ti Team:

Did you have TAS2505 linux driver code or mcu driver  code?

Thanks

CQ.LV

  • Hi,

    There is no linux driver specifically for TAS2505, although you could use TLV320DAC310x which is similar.
    Please take a look at this previous post: e2e.ti.com/.../2856357

    Please let us know if you have additional questions or comments on this.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis;

    Tas2505 according to the following settings, the output 9&12pin  can test 288KHZ PWM signal, but there is no sound. According to this settings, what frequency does the input MCLK BCLK WCLK need? Are there any good suggestions?18 pin  not connet to mcu

    4.0.7 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker

    Outputs

    # I2C Script to Setup the device in Playback Mode

    # Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY

    # This script set DAC output routed to HP Driver and Class-D driver via Mixer

    # # ==> comment delimiter

    # Page switch to Page 0

    W 30 00 00

    # Assert Software reset (P0, R1, D0=1)

    W 30 01 01

    # Page Switch to Page 1

    W 30 00 01

    # LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)

    W 30 02 00

    # Page switch to Page 0

    W 30 00 00

    # PLL_clkin = MCLK, codec_clkin = PLL_CLK, MCLK should be 11.2896MHz (P0, R4, D1-D0=03)

    w 30 04 03

    # Power up PLL, set P=1, R=1, (Page-0, Reg-5)

    w 30 05 91

    # Set J=4, (Page-0, Reg-6)

    w 30 06 04

    # D = 0000, D(13:8) = 0, (Page-0, Reg-7)

    w 30 07 00

    # D(7:0) = 0, (Page-0, Reg-8)

    w 30 08 00

    # add delay of 15 ms for PLL to lock

    d 15

    # DAC NDAC Powered up, NDAC=4 (P0, R11, D7=1, D6-D0=0000100)

    W 30 0B 84

    # DAC MDAC Powered up, MDAC=2 (P0, R12, D7=1, D6-D0=0000010)

    W 30 0C 82

    # DAC OSR(9:0)-> DOSR=128 (P0, R12, D1-D0=00)

    W 30 0D 00

    # DAC OSR(9:0)-> DOSR=128 (P0, R13, D7-D0=10000000)

    W 30 0E 80

    # Codec Interface control Word length = 16bits, BCLK&WCLK inputs, I2S mode. (P0, R27, D7-

    D6=00, D5-D4=00, D3-D2=00)

    W 30 1B 00

    # Data slot offset 00 (P0, R28, D7-D0=0000)

    W 30 1C 00

    # Dac Instruction programming PRB #2 for Mono routing. Type interpolation (x8) and 3 programmable

    Biquads. (P0, R60, D4-D0=0010)

    W 30 3C 02

    # Page Switch to Page 1

    W 30 00 01

    # Master Reference Powered on (P1, R1, D4=1)

    W 30 01 10

    # Output common mode for DAC set to 0.9V (default) (P1, R10)

    W 30 0A 00

    # Mixer P output is connected to HP Out Mixer (P1, R12, D2=1)

    w 30 0C 04

    # HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000)

    W 30 16 00

    # No need to enable Mixer M and Mixer P, AINL Voulme, 0dB Gain (P1, R24, D7=1, D6-D0=0000000)

    W 30 18 00

    # Power up HP (P1, R9, D5=1)

    w 30 09 20

    # Unmute HP with 0dB gain (P1, R16, D4=1)

    w 30 10 00

    # SPK attn. Gain =0dB (P1, R46, D6-D0=000000)

    W 30 2E 00

    # SPK driver Gain=6.0dB (P1, R48, D6-D4=001)

    W 30 30 10

    # SPK powered up (P1, R45, D1=1)

    W 30 2D 02

    # Page switch to Page 0

    W 30 00 00

    # DAC powered up, Soft step 1 per Fs. (P0, R63, D7=1, D5-D4=01, D3-D2=00, D1-D0=00)

    W 30 3F 90

    # DAC digital gain 0dB (P0, R65, D7-D0=00000000)

    W 30 41 00

    # DAC volume not muted. (P0, R64, D3=0, D2=1)

    W 30 40 04

    #


  • Hi, 

    I would recommend the following clock values:

    MCLK = 11.2896 MHz
    BCLK = 2.8224 MHz
    WCLK = 44.1KHz

    Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.