LM49350: PLL minimum reference clk frequency

Erkka, 

The PLL input must be 0.5-50Mhz, and the Phase Comparator frequency must be 0.7 - 5Mhz,   and in between there is the M divider. 

lets take an example from the Datasheet:

the final line of Table 7 shows a PLL input of 19.8Mhz, 

the M value is 16

The N value is 147

the P Value is 16.5

19.8Mhz / 16 = 1.2375Mhz.   This is the phase comparator frequency. 

multiply this result by N/P  and you get Fout = 11.025Mhz.  

does that make sense?

best regards,

-Steve Wilson