• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 32 subscribers
  • Views 543 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320ADC5140: Abrupt Power Down Sequence Violation

Sasi Sekaran Sundaresan
Prodigy 20 points

Part Number: TLV320ADC5140

As per the datasheet for TLV320ADC5140 there exists a power down SPEC t3 & t4 which mandates a minimum of 100us delay when P0_R5_D[3:2] is 0x0 and 10ms when P0_R5_D[3:2] is set to anything else, between RESET & IOVDD/AVDD (refer highlighted portion in snapshot below), for an abrupt hardware power down. In case our case we see ~240ms violation for both t3 & ~170ms for t4 (Refer attached images). In our case we have set P0_R5_D[3:2] to 0x10. Can you pls help provide explanation on the following,

  • Impact of this SPEC violation ?
  • Can it cause any latch up problems ?
  • Impact on momentary power cycle ?
  • Potential Solution without any design change ?
  • Would u recommend us to set P0_R5_D[3:2] to 0x00, since this will reduce the requirement to 100us ?

I have sent the scope shots in separate email.

  • 0
    TI__Mastermind 30240 points

    Sasi, 

    I'll take a look at the image you sent and get back to you.  I may need to loop in the design team.  

    best regards

    -Steve Wilson

  • 0 in reply to Uttam Agarwal
    TI__Intellectual 800 points

    Hi Sasi/Steve,

    I have attached the image which Sasi sent us over email. This is for future reference. 

    Based on device internal architecture used, we don't see any issue for all supplies sudden shut-down, provided the re-power of the supplies occur after few 100'ms and with SHDNZ pin kept low and following proper power-up sequence for AVDD, IOVDD and SHDNZ release as described in datasheet. Infact, this kind of stress test has already been done during our device validation and char.

    SHDNZ pin has a fail-safe IO and has no diode to either AVDD or IOVDD therefore powering down together with AVDD and IOVDD is fine and we don't expect any latch-up or device damage/reliability issue for this sudden power-down. 

    If the re-power of the supplies occur after few 100'ms and with SHDNZ pin kept low and following proper power-up sequence for AVDD, IOVDD and SHDNZ release as described in datasheet then we don't expect any functional issue in device operation.

    Yes, it would be recommended to configure P0_R5_D[3:2] to 0x00 so that the device can react fast on shutdown pin. Though this is not must if the re-power of the supplies occur after few 100'ms and with SHDNZ pin kept low and following proper power-up sequence for AVDD, IOVDD and SHDNZ release as described in datasheet.

     

    Let us know if this answer the query you have raised.

     

    - Uttam Agarwal

    System Engineer

  • 0 in reply to Uttam Agarwal
    Prodigy 20 points

    Hi Uttam,

    Based on our last sync up, my understanding is even if P0_R5_D[3:2] is not programmed to 0x00, still the device can support a WC power cycle of 30ms. is that statement correct ?

    Thanks,

    Sasi

  • 0 in reply to Sasi Sekaran Sundaresan
    TI__Intellectual 800 points

    Hi Sasi,

    If P0_R5_D[3:2] is not programmed to 0x00, then generally speaking if the re-power of the supplies occur after ~30ms and with SHDNZ pin kept low and following proper power-up sequence for AVDD, IOVDD and SHDNZ release as described in datasheet then the device mostly should recover however for robust and reliable option, we would recommend either program P0_R5_D[3:2] = 00 or wait for atleast ~100ms before re-power of the supplies.

     

    Regards,

    Uttam