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TLV320AIC3105: ADC Stops working on Overflow

jerome d.
Expert 1325 points
Part Number: TLV320AIC3105

Dear all
I'm using TLV320AIC3105 in my product and I noticed the following :


When Left/Right-ADC PGA Gain Control Registers (reg 15 and 16) programmed value are higher than about 50 (7bits), the ADC stops recording.
I suppose an overflow condition occurs at that time.
Reducing gain allows to make the ADC working again.

Is this the expected behavior ?
If so, what would be the workaround to allow the ADC working even if an overflow occurred ? I do not want to have to read periodically overflow registers.

Those gain registers are accepting 7bits gain from 0 to 127, and I cannot program the full 7bits range due to the above issue.

Any help would be greatly appreciated.
Thanks
Jerome

  • 0
    TI__Prodigy 150 points

    Hi Jerome,

    You may be violating the ADC input of 0.707 Vrms as stated in the datasheet.

    Currently, your PGA gain is 25dB, meaning the input to the PGA should be 40 mVrms.

    25dB = 20log(x)
    x = 17.8

    y*17.8 = 0.707 Vrms
    y = 40 mVrms

    Please verify your input values are within spec.

    Regards,

    Priscilla

  • 0 in reply to Priscilla Castillo
    Expert 1325 points

    Priscilla thanks for your answer.


    I know the ADC overloads, my question is "Is it normal the ADC stops working when it overloads ?".
    I'm inputing a pure sine wave at 440Hz, I'm expecting to record a clipped sine wave when the ADC overloads, but here I'm no longer recording any signal when increasing gain.
    Thanks

    Jerome

  • 0 in reply to jerome d.
    TI__Prodigy 150 points

    Hi Jerome,

    The device should not automatically disable when the ADC overflows. Can you please read registers 15, 16, 19, and 22 to see if the ADCs are still powered on, or if the PGAs are muted?

    Regards,

    Priscilla

  • 0 in reply to Priscilla Castillo
    Expert 1325 points

    Could you please clarify the following from 3105 datasheet ?

    1) Table 69. Page 0/Register 63: PGA_R to HPROUT Volume Control Register
    The datasheet is messy on this page.

    2) Page 37 Chapter 10.3.7 Input Impedance and VCM Control

    "Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input voltage of the ADC PGA (which is determined by an internal bandgap voltage reference). This is useful to keep the ac-coupling capacitors connected to analog inputs biased up at a normal dc level, thus avoiding the need for them to charge up suddenly when the input is changed from being unselected to selected for connection to an ADC PGA. This option is controlled in page 0, registers 20 and 23. The user should ensure this option is disabled when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, because it can corrupt the recorded input signal if left operational when an input is selected."

    Does this mean Bit 2 of registers 20 and 23 should be set to 1 if there is NO input connected to the the ADC first stage PGA (before the mixer), and should be set to zero as soon as one input or more are used ?
    In other words, if at least one input is connected to its PGA before the mixer, those D2 bits and registers 20 and 23 must be set to zero ?

    Thanks 




    Thanks

  • 0 in reply to jerome d.
    TI__Prodigy 150 points

    Hi Jerome,

     

    Please see my responses below:

    1.   Registers 59 and 61 are in correct formatting, and registers 60, 62, and 63 should match them. So, for Page 0/Register 63 it will be as follows:

    Table 69. Page 0/Register 63: PGA_R to HPROUT Volume Control Register

    BIT

    READ/

    WRITE

    RESET VALUE

    DESCRIPTION

    D7

    R/W

    0

    PGA_R Output Routing Control

    0: PGA_R is not routed to HPROUT.

    1: PGA_R is routed to HPROUT.

    D6 – D0

    R/W

    000 000

    PGA_R to HPROUT Analog Volume Control

    For 7-bit register setting versus analog gain values, see Table 50.

    2.      No, it will weakly bias the input pins to the common mode voltage. D2 can remain 1 all the time. Consider the image below:


     

    All unused inputs are connected to VCM. Mic2L is connected to the right PGA,  and because internally the PGA is a differential input (even on the AIC3105) the VCM is connected to the negative input with the same resistance as Mic2L. The weakly biased unused input has no interaction with the inputs that are active, or the PGA.