TPA3255: Can't determine failure cause for RESET input pin showing low resistance (6-30 ohms) on some units

Hi Peter,

Do you see the Fault pin go low as well as the issues that you are describing with the RESET pin? 

Regards,

Robert Clifton

On the damaged TPA3255: CLIP_OTW is 14 ohm to GND,  FAULT is 546 ohms to GND. The FAULT signal never goes high. This is complicated because the RESET signal is 6 ohms to GND, so the buffer can't provide enough current to drive RESET  high. The RESET signal can only present 0.7V to the input. When I do this, the FAULT signal changes from 0.047V to 0.70V.  Generally, I see the 12V current draw 200-300 mA higher in this damaged condition over the value expected when the RESET signal is not high (in a healthy TPA3255).

Hi Peter,

Interesting. When RESET is low the device forces the FAULT pin to go high. But from what you are saying that's not the case. Are you able to provide a schematic just concerning the amplifier? 

Thanks,

Robert Clifton

Robert,

Thank you for your help within this forum and for the outside assistance.   I've had a week of full volume/power testing on the circuits with no issues related to that testing that I'm aware of at this time.  I still see a failure on a unit that was not going through the full power tests, but just low power software integration. The same 3 pins are affected:RESET, FAULT, & CLIP_OTW. As explained above, these are buffered I/O from a processor on another board with a short run ~2" on an interface cable.

My question is: the 52V PVDD supply ramps up as so: 0-15V slowly (minutes), then 15-18.5V (value depending on S/W, but slow also in minutes), finally ~15-52V in mS. The VDD supply (~12V) is always present on PVDD ramp up, and comes up quickly (in mS).

The uP GPio interfacing with the 3 signals:

As soon as SYS_RESET* is de-asserted the processor applies a default state to the GPIO(s).  The default state is listed below. 

• P_AMP_CLIP_OTW* is a high impedance input with a ~35k Ohm internal pulldown.
• P_AMP_FAULT* is a high impedance input with a ~35k Ohm internal pulldown.
• P_AUDIO_RESET* is a high impedance input with a ~35k Ohm internal pulldown.

 Once the O/S starts to load, the device tree takes over control of the GPIO.  The device tree applies the following settings to the GPIO(s)

• P_AMP_CLIP_OTW* is an input with pullups and pulldowns disabled
• P_AMP_FAULT* is an input with pullups and pulldowns disabled
• P_AUDIO_RESET* is an output, pullups/pulldowns disabled, value is set to low by default

After the O/S loads we export the GPIO(s) to userspace and initializes them via HW initialization SW.

• P_AMP_CLIP_OTW* is an input with pullups and pulldowns disabled
• P_AMP_FAULT* is an input with pullups and pulldowns disabled
• P_AUDIO_RESET* is an output, pullups/pulldowns disabled, value is set to low by default.

 The application SW then controls each I/O based on normal system operation. We did have a software problem where on shutdown, the uP kept wanting to reboot over and over as the power bus it was using ramped down slowly (minutes). That is being corrected but the bug was in place when the unit in question was damaged.

When the circuits power down, the 52V bus will stay up (for hours) but may slowly decay over minutes-hours. At the same time the 12V is removed quickly (in mS). The uP on the other board is powered indirectly from the same power source as the 52V, so it remains powered. The RESET line may or may not provide a HIGH into the TPA3255 during this time. Can the TPA3255 be damaged if the 12V at TPA3255 pin 2 (also pin1 & 22)  is not present but the 52V is? Can the TPA3255 be damaged if the RESET signal is driven HIGH (or low) with the 12V not present?

@ Robert  and @Peter , I have some issue to use such kind of IC in 60 Hz transformer.

Kindly help me here,https://e2e.ti.com/support/audio/f/6/t/842164

Hi Peter, 

Was this unit already having issues or was this a brand new unit that was also confirmed to be working at some time? 

I don't believe that the RESET pin being high would be an issue when GVDD is not present. GVDD is for the gate drive voltage supply. When GVDD is off the device should just enter hi-z and Fault pin going low. Are you seeing the Fault pin going low when GVDD loses power?

Regards,

Robert Clifton

Robert,

This third unit was basically new, but it had some runtime and possible repair history.  At the start of the verification of this unit I checked that the RESET, FAULT and CLIP_OTW signals read to GND: 47.5K ext pulldown resistor; ~30K PU internal resistor; ~30K PU internal resistor. The buffers on the uP CCA had normal voltage readings on both sides of the buffer. When it was time to play the audio file, all 3 signals read ~3.3V indicating the system was ready to play audio.  

After several firmware/software changes with this unit involving several power on-off cycles, the voltage readings on the 3 signals changed to indicate a failure. The RESET line buffer output read 1.7V (should be 3.3V) and the other two signal were ~0.5V (should be 3.3V). The TPA3255 measured: 47.5K (with Ext pulldown); FAULT=~300 ohm; CLIP_OTW=~500 ohm.  The dual buffer on the FAULT and CLIP_OTW was damaged (would not go HIGH when interface cable disconnected). 

Additional checking found that on powerdowns, the uP board would stay powered and providing a RESET* HIGH for 5-10 seconds into the unpowered (12V not present into VDD and GVDD pins) digital input of the TPA3255. My concern is that the RESET* line is being driven and the current is flowing through the ESD diodes to where ever, but a high enough current to damage the ESD diode(s) over time. When the TPA 3255 and buffer were replaced, the unit worked OK. I'm placing 10K series resistors in-line with the 3 signals (RESET, FAULT and CLIP_OTW) to protect the buffer and audio amp.       See Fairchild App note AN-376 P.10-12 to see my concern. This app note was from 1984, so I'm not sure it is applicable to the TPA3255 input structure, but helps explain my thought process.